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A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation Journal article
Zhang, Ran, Cen, Xueru, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Martins, Rui P., Sin, Sai Weng. A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, 1-13.
Authors:  Zhang, Ran;  Cen, Xueru;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2025/01/22
Dac Driver  Dynamic Amplifier  Machine Learning (Ml)  Mixed-signal Multiply-and-accumulate (Mac)  Multi-bit Neural Network  
A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC Journal article
Zhao, Hongzhi, Zhang, Minglei, Zhu,Yan, Martins, R. P., Chan,Chi Hang. A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3586-3597.
Authors:  Zhao, Hongzhi;  Zhang, Minglei;  Zhu,Yan;  Martins, R. P.;  Chan,Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/29
Analog-to-digital Converter (Adc)  Multi-bit/cycle Successive-approximation Register (Sar) Adc  Time-domain Quantization  Voltage-to-time (V2t) Buffer  Linearization  
A Two-phase Multi-bit Incremental ADC with Variable Loop Order Journal article
Chen,Kaiquan, Wang,Biao, Liu,Yan, Ye,Fan, Sin,Sai Weng, Wang,Guoxing, Lian,Yong, Qi,Liang. A Two-phase Multi-bit Incremental ADC with Variable Loop Order[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(8), 2724-2728.
Authors:  Chen,Kaiquan;  Wang,Biao;  Liu,Yan;  Ye,Fan;  Sin,Sai Weng; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2023/08/03
Circuits And Systems  Variable Loop Order  Multi-bit Quantizer  Dwa Effectiveness  Noise Penalty  
Angular Domain Channel Estimation for mmWave Massive MIMO with One-Bit ADCs/DACs Journal article
Xu, Liangyuan, Qian, Cheng, Gao, Feifei, Zhang, Wei, Ma, Shaodan. Angular Domain Channel Estimation for mmWave Massive MIMO with One-Bit ADCs/DACs[J]. IEEE Transactions on Wireless Communications, 2021, 20(2), 969-982.
Authors:  Xu, Liangyuan;  Qian, Cheng;  Gao, Feifei;  Zhang, Wei;  Ma, Shaodan
Favorite | TC[WOS]:17 TC[Scopus]:21  IF:8.9/8.6 | Submit date：2021/12/07
Angular Domain  Channel Estimation  Multi-user Massive Mimo  One-bit Analogto-digital Converter  One-bit Digital-to-analog Converter  Precoding  Uplink/downlink  
An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction Conference paper
Chongyao Xu, Jieyun Zhang, Man-Kay Law, Xiaojin Zhao, Pui-In Mak, Rui P. Martins. An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180584.
Authors:  Chongyao Xu;  Jieyun Zhang;  Man-Kay Law;  Xiaojin Zhao;  Pui-In Mak; et al.
Favorite | TC[WOS]:1 TC[Scopus]:5 | Submit date：2022/01/25
Multiplier  Multi-bit  Physical Unclonable Function  Path Delay Extraction  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite | TC[WOS]:48 TC[Scopus]:60  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Zhang, Wai-Hong, Seng-Pan, U., Martins, Rui Paulo. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(3), 850-860.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | TC[WOS]:62 TC[Scopus]:68  IF:4.6/5.6 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
Design of High-Speed, Power-efficient SAR-Type ADCs Thesis
Zhong, J. Y., Zhu, Y., Sin, S. W., U, S.P.. Design of High-Speed, Power-efficient SAR-Type ADCs[D], 2017.
Authors:  Zhong, J. Y.;  Zhu, Y.;  Sin, S. W.;  U, S.P.
Favorite |  | Submit date：2023/08/31
SAR ADC  Multi-Bit Conversion  Merged DAC Technique  Noise Analysis  
A high resolution multi-bit incremental converter insensitive to DAC mismatch error Conference paper
Biao Wang, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A high resolution multi-bit incremental converter insensitive to DAC mismatch error[C], 2016.
Authors:  Biao Wang;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | TC[WOS]:2 TC[Scopus]:8 | Submit date：2019/02/11
High Resolution  Incremental Converter  Multi-bit Quantizer  Insensitive To Dac Mismatch