A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS

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	A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS
	Wang, B.; Sin, S. W.; U, S.P.; Maloberti, F.; Martins, R. P.
	2019-04-01
Source Publication	IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI)
ISSN	0018-9200
Pages	1161-1172
Abstract	This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling path is then enabled in the exponential phase thus boosting the SQNR exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the 1st order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65nm CMOS under 1.2V supply, the ADC achieves an SNDR/DR of 100.8dB/101.8dB with 20kHz BW, 550μW & 0.134mm2, resulting in Walden/Schreier FoMW/FoMS of 153fJ/176.4dB, respectively. The differential and integral nonlinearities are +0.27/-0.27 and +0.84/-0.81 LSBs, respectively.
Keyword	Analog-to-digital Converter Iadc Incremental Adc Sigma-delta Linear Exponential Accumulation Two-phase Multi-bit Mismatch Error Dynamic Element Matching (Dem) Data Weighting Average (Dwa) High Linearity Notch
URL	View the original
Language	英語English
The Source to Article	PB_Publication
Document Type	Journal article
Collection	University of Macau
Corresponding Author	Sin, S. W.
Recommended Citation GB/T 7714	Wang, B.,Sin, S. W.,U, S.P.,et al. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
APA	Wang, B.., Sin, S. W.., U, S.P.., Maloberti, F.., & Martins, R. P. (2019). A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 1161-1172.
MLA	Wang, B.,et al."A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS".IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI) (2019):1161-1172.

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