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An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction
Chongyao Xu1; Jieyun Zhang1; Man-Kay Law1; Xiaojin Zhao2; Pui-In Mak1; Rui P. Martins1,3
2020-10-01
Conference Name52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
Volume2020-October
Pages9180584
Conference Date12-14 October 2020
Conference PlaceSeville, Spain
CountrySpain
Publication PlaceIEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
PublisherIEEE
Abstract

This paper presents a digital N × N multiplier-based multi-bit strong physical unclonable function (PUF), which utilize the intrinsic path delay of the multiplier to achieve an approximated 1 : 2N^2 average challenge-to-response extraction to effectively increase the number of PUF responses. The PUF Extractor triggers the digital multiplier, and further processes the multiplier intrinsic path delay through a time-to-digital converter (TDC). Implemented with Xilinx Artix-7 FPGAs using the automatic place and route function, the proposed strong PUF demonstrates a 64-bit challenge with 32-bit multipliers with an extra level of unpredictability for counterfeiting model-based machine learning attack. With an average of 1:2048 responses per challenge, measurement results show that the uniqueness is 53.16%, and the stability of up to 95.54%, respectively.

KeywordMultiplier Multi-bit Physical Unclonable Function Path Delay Extraction
DOI10.1109/ISCAS45731.2020.9180584
URLView the original
Indexed ByCPCI-S
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000696570700197
The Source to ArticlePB_Publication
Scopus ID2-s2.0-85109269133
Fulltext Access
Citation statistics
Document TypeConference paper
CollectionTHE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorMan-Kay Law
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China
2.College of Electronics and Information Engineering, Shenzhen University, Shenzhen, China
3.On leave from Instituto Superior Tecnico, Universidade de Lisboa, Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chongyao Xu,Jieyun Zhang,Man-Kay Law,et al. An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180584.
APA Chongyao Xu., Jieyun Zhang., Man-Kay Law., Xiaojin Zhao., Pui-In Mak., & Rui P. Martins (2020). An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction. Proceedings - IEEE International Symposium on Circuits and Systems, 2020-October, 9180584.
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