Residential College | false |
Status | 已發表Published |
An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction | |
Chongyao Xu1; Jieyun Zhang1; Man-Kay Law1; Xiaojin Zhao2; Pui-In Mak1; Rui P. Martins1,3 | |
2020-10-01 | |
Conference Name | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 |
Source Publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Volume | 2020-October |
Pages | 9180584 |
Conference Date | 12-14 October 2020 |
Conference Place | Seville, Spain |
Country | Spain |
Publication Place | IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA |
Publisher | IEEE |
Abstract | This paper presents a digital N × N multiplier-based multi-bit strong physical unclonable function (PUF), which utilize the intrinsic path delay of the multiplier to achieve an approximated 1 : 2N^2 average challenge-to-response extraction to effectively increase the number of PUF responses. The PUF Extractor triggers the digital multiplier, and further processes the multiplier intrinsic path delay through a time-to-digital converter (TDC). Implemented with Xilinx Artix-7 FPGAs using the automatic place and route function, the proposed strong PUF demonstrates a 64-bit challenge with 32-bit multipliers with an extra level of unpredictability for counterfeiting model-based machine learning attack. With an average of 1:2048 responses per challenge, measurement results show that the uniqueness is 53.16%, and the stability of up to 95.54%, respectively. |
Keyword | Multiplier Multi-bit Physical Unclonable Function Path Delay Extraction |
DOI | 10.1109/ISCAS45731.2020.9180584 |
URL | View the original |
Indexed By | CPCI-S |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000696570700197 |
The Source to Article | PB_Publication |
Scopus ID | 2-s2.0-85109269133 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Man-Kay Law |
Affiliation | 1.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China 2.College of Electronics and Information Engineering, Shenzhen University, Shenzhen, China 3.On leave from Instituto Superior Tecnico, Universidade de Lisboa, Portugal |
First Author Affilication | University of Macau |
Corresponding Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Chongyao Xu,Jieyun Zhang,Man-Kay Law,et al. An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180584. |
APA | Chongyao Xu., Jieyun Zhang., Man-Kay Law., Xiaojin Zhao., Pui-In Mak., & Rui P. Martins (2020). An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction. Proceedings - IEEE International Symposium on Circuits and Systems, 2020-October, 9180584. |
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