This paper presents a second order multi-bit incremental analog-to-digital converter with two-phase feedback DAC control logic, insensitive to capacitor mismatches and with enhanced performance in multi-bit implementation. Besides, the proposed technique eliminates the complexity of dynamic element matching and relaxes the Op-amp’s settling time. Behavioral simulations show that it can achieve ૚૚૞. ૞૞ dB SNDR at ૚૛ૡ clock cycles using a ૠ -bit quantizer without dynamic element matching.