| Status | 已發表Published |
| Title | Design of High-Speed, Power-efficient SAR-Type ADCs |
| Author | Zhong, J. Y.; Zhu, Y.  ; Sin, S. W.; U, S.P.
|
| Date Issued | 2017-01-31 |
| Keyword | SAR ADC Multi-Bit Conversion Merged DAC Technique Noise Analysis |
| Abstract | SAR analog-to-digital converters (ADCs) are well known for their excellent power- and area- efficiencies as well as good technology scaling characteristics. However, its speed and resolution are limited (ENOB≤10b) due to capacitor matching, comparator noise and the use of a sequential conversion algorithm. Pipeline ADCs can achieve high speeds but dissipate considerable power in static opamps and require complex calibration schemes to achieve high accuracy in nanometer CMOS processes. The pipelined-SAR ADC that exploits the high speed of pipeline and low power of SAR, has recently emerged as an excellent power-efficient architecture targeted for resolution of ≧12-bit and speed of ≧100 MS/s. This dissertation investigates the fundamental limitations and design challenges of pipelined-SAR ADCs, which includes the thermal and reference noise effects, the sampling and conversion nonlinearity as well as the effective calibration schemes with low design overhead. The designs of high performance pipelined-SAR ADC integrated with novel circuit techniques for sampling front-end noise and linearity optimization, stage-gain error cancellation, conversion power reduction and speed enhancement are presented. The experimental results show that with the proposed techniques, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency and minimized chip-area are accomplished simultaneously. In the first design, an inter-stage gain error calibration method devoted to correct the residue gain errors induced by the parasitic effects, non-ideal opamp gain and capacitor mismatch, and also the mismatches for supply-derived reference voltages between two stages is proposed. The calibration reuses the SAR ADC to estimate the error and compensates it in the 2nd-stage DAC in 2 cycles, and it is implemented in a pipelined-SAR ADC which achieves 10-bit 470-MS/s in 65nm CMOS process with FoM of 31.5 fJ/conv.-step. The second design presents a 12b 180 MS/s 0.068 mm2 2×TI pipelined-SAR ADC with fully embedded gain and offset calibrations. The inter-stage gain error caused by the open-loop residue amplifier is corrected by the proposed binary-search gain calibration technique. The calibration is fully integrated in the 2nd-stage SAR ADC for compact area. The noise performance is improved by implementing a merged-residue-DAC operation in the 1st-stage ADC. The dual-phase bootstrap technique is proposed to improve the sampling linearity in the partial interleaving architecture. With the use of multi-merging switching method, the switching power is reduced and the speed is increased in the 1st-stage 2b/cycle SA conversion. The measurement results of the ADC prototype in 65nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio (SNDR) from 51.5 dB to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step. |
| Language | 英語English |
| PUB ID | 38599 |
| Document Type | Thesis |
| Collection | INSTITUTE OF MICROELECTRONICS |
| Corresponding Author | Zhu, Y. |
| Recommended Citation GB/T 7714 | Zhong, J. Y.,Zhu, Y.,Sin, S. W.,et al. Design of High-Speed, Power-efficient SAR-Type ADCs[D], 2017. |
| Files in This Item: | There are no files associated with this item. | |||||
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment