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A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
Advanced Techniques in Analog to Digital Converters Thesis
Xing, D., U, S.P., Zhu, Y., Sin, S. W.. Advanced Techniques in Analog to Digital Converters[D], 2018.
Authors:  Xing, D.;  U, S.P.;  Zhu, Y.;  Sin, S. W.
Favorite |  | Submit date：2023/08/31
Analog to Digital Converters  
A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS Conference paper
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS[C], US:IEEE, 2018.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
Incremental Converter  Analog to Digital Converter  ADC  
A 430frms 2.4GHz Ring-Oscillator PLL with Backend Discrete-Time Phase Noise Cancellation Achieving 240.5dB Jitter-FoM Presentation
会议地点: 2018 International Solid-State Circuits Conference, San Francisco, 报告日期: 2018-02-17
Authors:  Yang, X.F.;  Zhu, Y.;  Chan, C. H.;  Wang, G. C.;  U, S.P.
Favorite |  | Submit date：2023/08/31
A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing Journal article
Qi, L., Sin, W., U, S.P., Maloberti, F., Martins, R. P.. A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing[J]. IEEE Transactions on Circuits and Systems I - Regular Papers, 2017, 2641-2654.
Authors:  Qi, L.;  Sin, W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/24
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Δς) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Sar Quantizer  
Digital Assisted Techniques for Bridge DAC Capacitor Mismatch Calibration in SAR ADC Thesis
Wang , G.C., Zhu, Y., Chan, C. H., U, S.P.. Digital Assisted Techniques for Bridge DAC Capacitor Mismatch Calibration in SAR ADC[D], 2017.
Authors:  Wang , G.C.;  Zhu, Y.;  Chan, C. H.;  U, S.P.
Favorite |  | Submit date：2023/08/31
Bridge DAC  Capacitor Mismatch Calibration  SAR ADC  
Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications Journal article
Jiang, D., Sin, S. W., U, S.P., Martins, R. P., Maloberti, F.. Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications[J]. Electronics Letters, 2017, 506-508.
Authors:  Jiang, D.;  Sin, S. W.;  U, S.P.;  Martins, R. P.;  Maloberti, F.
Favorite |   IF:0.7/0.9 | Submit date：2022/01/24
band-pass filters  circuit simulation  modulators  radio receivers  sigma-delta modulation  software radio  table lookup  
Design of High-Speed, Power-efficient SAR-Type ADCs Thesis
Zhong, J. Y., Zhu, Y., Sin, S. W., U, S.P.. Design of High-Speed, Power-efficient SAR-Type ADCs[D], 2017.
Authors:  Zhong, J. Y.;  Zhu, Y.;  Sin, S. W.;  U, S.P.
Favorite |  | Submit date：2023/08/31
SAR ADC  Multi-Bit Conversion  Merged DAC Technique  Noise Analysis  
Active–Passive ΔΣ Modulator for High-Resolution and Low-Power Applications Journal article
Hussain, A., Sin, S. W., Chan, C. H., U, S.P., Maloberti, F., Martins, R. P.. Active–Passive ΔΣ Modulator for High-Resolution and Low-Power Applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 364-374.
Authors:  Hussain, A.;  Sin, S. W.;  Chan, C. H.;  U, S.P.;  Maloberti, F.; et al.
Favorite |   IF:2.8/2.8 | Submit date：2022/01/24
Delta-sigma Modulator ( m)  Discrete Time (Dt)  Low-gain-amplifier-based Switched-capacitor (Sc) Integrator  Noise Shaping  Passive Sc Integrator  
A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS Journal article
Liu, J., Chan, C.H., Sin, S. W., U, S.P., Martins, R. P.. A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 395-404.
Authors:  Liu, J.;  Chan, C.H.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite |   IF:0.5/0.3 | Submit date：2022/01/24
Flash ADC  time comparator  4x time-domain interpolation  SR-latch