A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS

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	A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS
	Liu, J.; Chan, C.H.; Sin, S. W.; U, S.P.; Martins, R. P.
	2016-08-01
Source Publication	Journal of Semiconductor Technology and Science
ISSN	1598-1657
Pages	395-404
Abstract	A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the 2N-2 comparators needs to be calibrated. The offset in SR-latches is within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.
Keyword	Flash ADC time comparator 4x time-domain interpolation SR-latch
Language	英語English
The Source to Article	PB_Publication
PUB ID	28748
Document Type	Journal article
Collection	DEPARTMENT OF PORTUGUESE
Corresponding Author	Chan, C.H.
Recommended Citation GB/T 7714	Liu, J.,Chan, C.H.,Sin, S. W.,et al. A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 395-404.
APA	Liu, J.., Chan, C.H.., Sin, S. W.., U, S.P.., & Martins, R. P. (2016). A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS. Journal of Semiconductor Technology and Science, 395-404.
MLA	Liu, J.,et al."A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS".Journal of Semiconductor Technology and Science (2016):395-404.

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