| Status | 已發表Published |
| A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS | |
Wang, B. ; Sin, S. W. ; U, S.P.; Maloberti, F.; Martins, R. P.
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| 2018-06-18 | |
| Source Publication | IEEE Symposium on VLSI Circuits
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| Publication Place | US |
| Publisher | IEEE |
| Abstract | This paper presents an incremental A/D converter with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise coupling path is then enabled in the exponential phase thus boosting the SQNR exponentially with a few number of clock cycles. The uniform-exponential weight function allows data weighted averaging (DWA) to work well suppressing the DAC mismatch error. Fabricated in 65nm CMOS under 1.2V supply, the ADC achieves an SNDR/DR of 100.8dB/101.8dB with 20kHz BW, 550μW & 0.134mm2, resulting in FoMW and FoMS of 153fJ/176.4dB (SNDR), respectively. |
| Keyword | Incremental Converter Analog to Digital Converter ADC |
| URL | View the original |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 40016 |
| Document Type | Conference paper |
| Collection | Institute of Chinese Medical Sciences |
| Corresponding Author | Sin, S. W. |
| Recommended Citation GB/T 7714 | Wang, B.,Sin, S. W.,U, S.P.,et al. A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS[C], US:IEEE, 2018. |
| APA | Wang, B.., Sin, S. W.., U, S.P.., Maloberti, F.., & Martins, R. P. (2018). A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS. IEEE Symposium on VLSI Circuits. |
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