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A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:10  IF:5.2/4.5 | Submit date：2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique Journal article
Yuan Liang, Chirn Chye Boon, Gengzhen Qi, Giannino Dziallas, Dietmar Kissinger, Herman Jalli Ng, Pui-In Mak, Yong Wang. A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique[J]. IEEE Transactions on Microwave Theory and Techniques, 2022, 70(5), 2642-2657.
Authors:  Yuan Liang;  Chirn Chye Boon;  Gengzhen Qi;  Giannino Dziallas;  Dietmar Kissinger; et al.
Favorite | TC[WOS]:11 TC[Scopus]:23  IF:4.1/4.2 | Submit date：2022/05/17
Bicmos  Exclusive-or (Xor) Gate  Frequency Detector  Harmonic Cancellation  Jitter  Lock Detector  Phase Detector (Pd)  Phase Noise  Phase-locked Loop (Pll)  Terahertz (Thz)  
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM Journal article
Yang, Zunsong, Chen, Yong, Yuan, Jia, Mak, Pui In, Martins, Rui P.. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 30(2), 238-242.
Authors:  Yang, Zunsong;  Chen, Yong;  Yuan, Jia;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:20 TC[Scopus]:21  IF:2.8/2.8 | Submit date：2022/03/04
Binary Frequency Shift Keying (Bfsk)  Frequency-locked Loop (Fll)  Integer-n  Phase Detector (Pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Push-pull  Reference (Ref) Spur  Sub-sampling (Ss)  Voltage-controlled Oscillator (Vco)  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
Zunsong Yang, Yong Chen, Pui In Mak, Rui P. Martins. A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68(6), 2307-2316.
Authors:  Zunsong Yang;  Yong Chen;  Pui In Mak;  Rui P. Martins
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Cmos  Current-reuse Sampling Phase Detector (Crs-pd)  Integrated Jitter  Loop Filter (Lf)  Master-slave Sampling Filter (Mssf)  Master-slave Sampling Phase Detector (Mss-pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Type-i  Type-ii  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:21 TC[Scopus]:21  IF:5.2/4.5 | Submit date：2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[Scopus]:16 | Submit date：2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
Yang,Zunsong, Chen,Yong, Yang,Shiheng, Mak,Pui In, Martins,Rui P.. A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector[J]. IEEE Access, 2019, 8, 2222-2232.
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:19 TC[Scopus]:20  IF:3.4/3.7 | Submit date：2021/03/09
Cmos  Dual Loop  Phase-locked Loop (Pll)  Frequency Detector (Fd)  Phase Detector (Pd)  Figure-of-merit (Fom)  Millimeter (Mm)-wave  Voltage-to-current Converter (Vic)  Voltage-controlled Oscillator (Vco)  Divider-by-4  Dynamic Latch