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| A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS | |
Zhao,Xiaoteng1; Chen,Yong2  ; Mak,Pui In1; Martins,Rui P.3
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| 2021-01 | |
| Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers
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| ISSN | 1549-8328 |
| Volume | 68Issue:1Pages:89-102 |
| Abstract | This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/ PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is <0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes. |
| Keyword | Bang- Bang Clock And Data Recovery (Bbcdr) Bang-bang Phase Detector (Bbpd) Cmos Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8) Half Rate Hogge And alexAnder Pd Jitter Tolerance (Jtol). Jitter Transfer Function (Jtf) Non-return-to-zero (Nrz) Strongarm Comparator |
| DOI | 10.1109/TCSI.2020.3038865 |
| URL | View the original |
| Indexed By | SCIE ; CPCI-S |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000607383700010 |
| Scopus ID | 2-s2.0-85097923526 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Journal article |
| Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS |
| Corresponding Author | Chen,Yong |
| Affiliation | 1.Xiaoteng Zhao, Yong Chen, and Pui-In Mak are with the State-Key Laboratory of Analog and Mixed-Signal VLSI/IME, University of Macau, Macau, China, and also with the DECE/Faculty of Science and Technology, University of Macau, Macau, China. 2.Xiaoteng Zhao, Yong Chen, and Pui-In Mak are with the State-Key Laboratory of Analog and Mixed-Signal VLSI/IME, University of Macau, Macau, China, and also with the DECE/Faculty of Science and Technology, University of Macau, Macau, China (e-mail: [email protected]) 3.State-Key Laboratory of Analog and Mixed-Signal VLSI/IME, University of Macau, Macau, China, and also with the DECE/Faculty of Science and Technology, University of Macau, Macau, China, on leave from the Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal. |
| First Author Affilication | Faculty of Science and Technology |
| Corresponding Author Affilication | Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Zhao,Xiaoteng,Chen,Yong,Mak,Pui In,et al. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102. |
| APA | Zhao,Xiaoteng., Chen,Yong., Mak,Pui In., & Martins,Rui P. (2021). A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(1), 89-102. |
| MLA | Zhao,Xiaoteng,et al."A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS".IEEE Transactions on Circuits and Systems I: Regular Papers 68.1(2021):89-102. |
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