This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of -63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of -241.9 dB. With a 103-MHz reference input, a bandwidth of 20 MHz aids suppressing significantly the ring VCO's phase noise (PN), leading to an in-band PN of -116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2.