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A low dropout regulator with PSR under-48dB up to 20GHz for a SARADC reference buffer Conference paper
Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui P. Martins. A low dropout regulator with PSR under-48dB up to 20GHz for a SARADC reference buffer[C], 2022.
Authors:  Yi Zeng;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2023/03/06
Low Dropout Regulator (Ldo)  High Power Supply Rejection (Psr)  Reference Buffer  Successive-approximation-register (Sar)  Analog-to-digital Converter (Adc)  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
Zhang,Minglei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019, 54(12), 3396-3409.
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:27 TC[Scopus]:40  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Low Power Supply  Process  Voltage  And Temperature (Pvt) Robustness  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage-to-time Converter (Vtc)  
A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation Journal article
Lei, X.W., Zhu, Y., Chan, C. H., Martins, R. P.. A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS,, 2019, 3365-3372.
Authors:  Lei, X.W.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bluetooth low energy (BLE)  frequency-shift keying (FSK)  low power  phase ADC.  
A 4-b 7-μ W phase domain ADC with time domain reference generation for low-power FSK/PSK Demodulation Journal article
Lei,Xuewei, Chan,Chi Hang, Zhu,Yan, Martins,Rui Paulo. A 4-b 7-μ W phase domain ADC with time domain reference generation for low-power FSK/PSK Demodulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3365-3372.
Authors:  Lei,Xuewei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2021/03/09
Bluetooth Low Energy (Ble)  Frequency-shift Keying (Fsk)  Low Power  Phase Adc  
A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
Sunny S., Chen Y., Boon C.C.. A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications[J]. IEEE Sensors Journal, 2018, 18(11), 4553-4560.
Authors:  Sunny S.;  Chen Y.;  Boon C.C.
Favorite | TC[WOS]:18 TC[Scopus]:21  IF:4.3/4.2 | Submit date：2019/02/14
1.5-bit/cycle  Adc  Capacitive Digital-to-analog Converter (Cdac)  Cmos  Error Correction  Low Power  Medical Imaging  Redundancy  Sar  Successive Approximation Register  
Nano-Watt Class Energy-Efficient Capacitive Sensor Interface with On-Chip Temperature Drift Compensation Journal article
Tan-Tan Zhang, Man-Kay Law, Pui-In Mak, Mang-I Vai, Rui P. Martins. Nano-Watt Class Energy-Efficient Capacitive Sensor Interface with On-Chip Temperature Drift Compensation[J]. IEEE Sensors Journal, 2018, 18(7), 2870-2882.
Authors:  Tan-Tan Zhang;  Man-Kay Law;  Pui-In Mak;  Mang-I Vai;  Rui P. Martins
Favorite | TC[WOS]:17 TC[Scopus]:19 | Submit date：2019/02/11
Capacitive Sensor Interface  Energy Efficiency  High Accuracy  Mismatch Errors  Pressure Sensor  Temperature Compensation  Two-step Incremental-adc  Ultra-low Power  
A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems Conference paper
Tan-Tan Zhang, Man-Kay Law, Bo Wang, Pui-In Mak, Mang-I Vai, Rui P. Martins. A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems[C], 2018, 1-4.
Authors:  Tan-Tan Zhang;  Man-Kay Law;  Bo Wang;  Pui-In Mak;  Mang-I Vai; et al.
Favorite | TC[WOS]:3 TC[Scopus]:1 | Submit date：2019/02/11
Chopping  Dynamic Element Matching  Energy Efficiency  Incremental Adc  Sensor Interface  Two-step  Ultra-low-power  Vearable Sensing System  
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Wng Sin, Seng-Pan U, Rui Paulo Martins. A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64(7), 1684-1695.
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Wng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:23 TC[Scopus]:30 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC Journal article
Zhong, Jianyu, Zhu, Yan, Chan, Chi-Hang, Sin, Sai-Weng, U, Seng-Pan, Martins, Rui Paulo. A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(7), 1684-1695.
Authors:  Zhong, Jianyu;  Zhu, Yan;  Chan, Chi-Hang;  Sin, Sai-Weng;  U, Seng-Pan; et al.
Favorite | TC[WOS]:23 TC[Scopus]:30  IF:5.2/4.5 | Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Successive Approximation Architecture  Low Power  Switched-capacitor Circuits