This paper presents a high power supply rejection (PSR) low-dropout regulator (LDO) for the reference buffer of successive-Approximation-register (SAR) analog-To-digital converters (ADCs). The reference buffer provides a stable reference voltage for a capacitive digital-To-Analog converter (CDAC), but relies upon a clean power supply to maintain a high PSR ability and thereby a high settling accuracy. The proposed LDO consists of a replica feedback loop and supply noise coupling (SNC) circuit. The regulated output voltage of this LDO is 1. 2V as the power supply of the reference buffer. The simulation results demonstrate that the proposed technique improves the signal-To(noise and distortion) ratio (SNDR) from 46dB to 72dB in a 12 bits SAR ADC. The LDO with the SNC consumes 100\muA quiescent current with a power supply of 1.SV, verified in 65nm CMOS, where the SNC only takes 15\muA. The simulated PSR is better than-48dB up to 20GHz.