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A 167-μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO Journal article
Shao, Haijun, Martins, Rui P., Mak, Pui In. A 167-μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Shao, Haijun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/11/05
Adjacent Channel  Bluetooth Low Energy (Ble)  Cascaded  Cmos  Double Balanced  Figure Of Merit (Fom)  Hybrid Coupler  Noise Figure (Nf)  Notching  Out Of Band (Oob)  Passive Intensive  Phase Noise (Pn)  Quadrature  Signal-to-noise Ratio (Snr)  Spurious-free Dynamic Range (Sfdr)  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation Journal article
Han, Changxuan, Deng, Zhixian, Shu, Yiyang, Yin, Jun, Mak, Pui In, Luo, Xun. A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 71(1), 120-132.
Authors:  Han, Changxuan;  Deng, Zhixian;  Shu, Yiyang;  Yin, Jun;  Mak, Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2024/02/22
Low Noise Amplifier (Lna)  Millimeter-wave (Mm-wave)  Noise-cancelling  Phase And Amplitude Compensation  Receiver (Rx)  Wideband  
A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner Journal article
Fan, Chao, Zhao, Ya, Zhang, Yanlong, Yin, Jun, Geng, Li, Mak, Pui In. A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner[J]. IEEE Transactions on Circuits and Systems II - Express Briefs, 2022, 70(3), 865-869.
Authors:  Fan, Chao;  Zhao, Ya;  Zhang, Yanlong;  Yin, Jun;  Geng, Li; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2023/01/30
Cmos  Ring Voltage-controlled Oscillator (Rvco)  Phase Noise  Flicker Noise  1/f3 Phase Noise Corner  Inherent Low-frequency Output  Multi-phase Injection Locking (Mpil)  Clock Generation  
A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction Journal article
Xu, Tailong, Zhong, Shenke, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4774-4786.
Authors:  Xu, Tailong;  Zhong, Shenke;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2023/01/30
Gain-boosting  Low Jitter  Low Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Reference-sampling Phase Detector (Rspd)  Sampling Phase Detector (Spd)  Sub-sampling Phase Detector (Sspd)  Switched-capacitor Voltage Multiplier  
Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes - Fundamentals and Design Techniques Review article
2022
Authors:  Loo, Mikki How Wen;  Ramiah, Harikrishnan;  Lei, Ka Meng;  Lim, Chee Cheow;  Lai, Nai Shyan; et al.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:3.4/3.7 | Submit date：2022/09/09
Allan Deviation  Cmos  Figure-of-merit (Fom)  Frequency-locked-loop (Fll)  Internet-of-things (Iot)  Jitter  Phase Noise  Relaxation Oscillator (Rxo)  Ultra-low-power  Wakeup Timers  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
Chen, Peng, Meng, Xi, Yin, Jun, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(1), 51-63.
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:16 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Adpll  Bluetooth Le (bLe)  Dco  Fractionaln Pll  Phase Noise (Pn)  Tdc  Dtc  Inverse-class-f  Low Power  The Iot  
An Ultralow Phase Noise Eight-Core Fundamental 62-To-67-GHz VCO in 65-nm CMOS Journal article
Zhang, Jingzhi, Zhao, Chenxi, Wu, Yunqiu, Liu, Huihua, Zhu, Yan, Kang, Kai. An Ultralow Phase Noise Eight-Core Fundamental 62-To-67-GHz VCO in 65-nm CMOS[J]. IEEE Microwave and Wireless Components Letters, 2019, 29(2), 125-127.
Authors:  Zhang, Jingzhi;  Zhao, Chenxi;  Wu, Yunqiu;  Liu, Huihua;  Zhu, Yan; et al.
Favorite | TC[WOS]:15 TC[Scopus]:17  IF:2.9/3.0 | Submit date：2022/04/15
Coupled-vco  Fundamental  Low Phase Noise (Pn)  Mm-wave  Multicore  Scalable Layout  Vco-core  
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
Tongquan Jiang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(2), 157-161.
Authors:  Tongquan Jiang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:11 TC[Scopus]:13  IF:4.0/3.7 | Submit date：2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A sub-GHz multi-ISM-band ZigBee receiver using function-reuse and gain-boosted N-path techniques for IoT applications Journal article
Zhicheng Lin, Pui-In Mak, Rui P. Martins. A sub-GHz multi-ISM-band ZigBee receiver using function-reuse and gain-boosted N-path techniques for IoT applications[J]. IEEE Journal of Solid-State Circuits, 2014, 49(12), 2990-3004.
Authors:  Zhicheng Lin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:46 TC[Scopus]:54 | Submit date：2019/02/11
Blocker Nf  Cmos  Current Reuse  Iip3  Internet Of Things (Iot)  Ism  Linear Periodically Time-variant (Lptv)  Low-noise Amplifier (Lna)  Mixer  Noise Figure (Nf)  Out-of-band (Ob)  Phase Noise  Receiver  Ultra-low-power (Ulp)  Ultra-low-voltage (Ulv)  Voltage-control Led Oscillator (Vco)  Wireless  Zigbee