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A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling Conference paper
Wang, Qingxun, Pan, Yuhan, Chen, Kaiquan, Lin, Yu, Wang, Biao, Qi, Liang. A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling[C]:IEEE345 E 47TH ST, NEW YORK, NY 10017 USA, 2023.
Authors:  Wang, Qingxun;  Pan, Yuhan;  Chen, Kaiquan;  Lin, Yu;  Wang, Biao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/23
Incremental Analog-to-digital Converter (Iadc)  Linear-exponential  Second-order Noise Coupling (Nc)  The Effective Data Weighting Averaging (Dwa) And Suppression Of Thermal Noise  
L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs Journal article
Wang, Bo, Law, Man Kay, Schneider, Jens. L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs[J]. IEEE Transactions on Signal Processing, 2023, 71, 3229-3241.
Authors:  Wang, Bo;  Law, Man Kay;  Schneider, Jens
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:4.6/5.2 | Submit date：2024/02/22
Analog-to-digital Data Converter  Digital Linear Filter  Frequency Notch  Incremental Delta-sigma Adc  l  Reconstruction Filter  Thermal Noise Penalty  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
Jiang, D., Sin, S. W., Qi, L., Wang, G., Martins, R. P.. Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 129-139.
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback Conference paper
Wang, B., Law, M. K., Bermak, A.. On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180394.
Authors:  Wang, B.;  Law, M. K.;  Bermak, A.
Favorite | TC[WOS]:0  | Submit date：2022/08/01
Incremental Delta-sigma Analog-to-digital Converter  Fully Differential Idc  1.5-bit Feedback  Modulator Codeword  Time-domain Analysis  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite | TC[WOS]:44 TC[Scopus]:55  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase  
A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS Conference paper
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS[C], US:IEEE, 2018.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
Incremental Converter  Analog to Digital Converter  ADC  
A high resolution multi-bit incremental converter insensitive to DAC mismatch error Conference paper
Biao Wang, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A high resolution multi-bit incremental converter insensitive to DAC mismatch error[C], 2016.
Authors:  Biao Wang;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | TC[WOS]:2 TC[Scopus]:8 | Submit date：2019/02/11
High Resolution  Incremental Converter  Multi-bit Quantizer  Insensitive To Dac Mismatch  
A 1.1 μW CMOS smart temperature sensor with an inaccuracy of ±0.2 °C (3σ) for clinical temperature monitoring Journal article
Man-Kay Law, Sanfeng Lu, Tao Wu, Amine Bermak, Pui-In Mak, Rui P. Martins. A 1.1 μW CMOS smart temperature sensor with an inaccuracy of ±0.2 °C (3σ) for clinical temperature monitoring[J]. IEEE Sensors Journal, 2016, 16(8), 2272-2281.
Authors:  Man-Kay Law;  Sanfeng Lu;  Tao Wu;  Amine Bermak;  Pui-In Mak; et al.
Favorite | TC[WOS]:32 TC[Scopus]:43 | Submit date：2019/02/11
Smart Temperature Sensor  Ultra-low Power  High Accuracy  Incremental Analog-to-digital Converter (I-adc),  Multi-ratio Pre-gain  Block-based Data Weighted Averaging (Bdwa)  
A 1.1 µW CMOS Smart Temperature Sensor with an Inaccuracy of ±0.2oC (3σ) for Clinical Temperature Monitoring Journal article
Law, M. K., Lu, S., Wu, T., Bermak, A., Mak, P. I., Martins, R. P.. A 1.1 µW CMOS Smart Temperature Sensor with an Inaccuracy of ±0.2oC (3σ) for Clinical Temperature Monitoring[J]. IEEE Sensors Journal, 2016, 2272-2281.
Authors:  Law, M. K.;  Lu, S.;  Wu, T.;  Bermak, A.;  Mak, P. I.; et al.
Favorite |   IF:4.3/4.2 | Submit date：2022/01/24
Smart temperature sensor  ultra-low power  high accuracy  incremental analog-to-digital converter (I-ADC)  multi-ratio pre-gain  block-based data weighted averaging (BDWA)