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On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback
Wang, B.1; Law, M. K.2; Bermak, A.1
2020-10-01
Conference Name52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
VolumeVolume 2020-October
Pages9180394
Conference Date12-14 October 2020
Conference PlaceSeville, Spain
CountrySpain
Publication PlaceIEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
PublisherIEEE
Abstract

This paper presents the time-domain analysis of a fully differential incremental ΔΣ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, the quantization noise can be decreased by 4× for the 1st- and 2nd-order modulators analyzed in this paper, with very minor modifications on the modulator’s original digital controllers.

KeywordIncremental Delta-sigma Analog-to-digital Converter Fully Differential Idc 1.5-bit Feedback Modulator Codeword Time-domain Analysis
DOI10.1109/ISCAS45731.2020.9180394
URLView the original
Indexed ByCPCI-S
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000696570700007
The Source to ArticlePB_Publication
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Document TypeConference paper
CollectionTHE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)
INSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorWang, B.
Affiliation1.Division of Information and Computing Technology, College of Science and Engineering, Hamad Bin Khalifa University, Doha, Qatar
2.State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macau, China
Recommended Citation
GB/T 7714
Wang, B.,Law, M. K.,Bermak, A.. On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180394.
APA Wang, B.., Law, M. K.., & Bermak, A. (2020). On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback. Proceedings - IEEE International Symposium on Circuits and Systems, Volume 2020-October, 9180394.
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