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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration
Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:
Zhang, Hongshuai
;
Zhu, Yan
;
Chan, Chi Hang
;
Martins, Rui P.
Favorite
|
TC[WOS]:
8
TC[Scopus]:
10
IF:
4.6
/
5.6
|
Submit date:2022/05/13
Amplifier Linearity Enhancement
Analog-to-digital Converter (Adc)
Background Offset Calibration
Digital Reconstruction Filter
Dwa
Energy And Area Efficient
Inherent Gain Error Tolerant
Inter-stage Gain Error
Noise Shaping (Ns)
Oversampling
Partial Interleaving
Pipelined Successive Approximation (Sar)
Quantization Leakage Error
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC
Journal article
Wang G., Li C., Zhu Y., Zhong J., Lu Y., Chan C.-H., Martins R.P.. Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11), 3707-3719.
Authors:
Wang G.
;
Li C.
;
Zhu Y.
;
Zhong J.
;
Lu Y.
; et al.
Favorite
|
TC[WOS]:
5
TC[Scopus]:
5
|
Submit date:2019/02/11
Bridge Dac
Gain Error Calibration
Low-dropout (Ldo) Regulator
Sar Adc
Testing Signal Generation
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
Journal article
Wang, Guan Cheng, Zhu, Yan, Chan, Chi-Hang, Seng-Pan, U., Martins, Rui P.. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(11), 2279-2289.
Authors:
Wang, Guan Cheng
;
Zhu, Yan
;
Chan, Chi-Hang
;
Seng-Pan, U.
;
Martins, Rui P.
Favorite
|
TC[WOS]:
2
TC[Scopus]:
2
IF:
2.8
/
2.8
|
Submit date:2019/01/17
Bridge Digital-to-analog Converter (Dac)
Gain Error Calibration
Successive Approximation Register (Sar)
Analog-to-digital Converters (Adcs)
Testing Signal Generation (Tsg)
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC
Conference paper
Wang, Guancheng, Li, Cheng, Zhu, Yan, Zhong, Jianyu, Lu, Yan, Chan, Chi-Hang, Martins, Rui P.. Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC[C], 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018, 3707-3719.
Authors:
Wang, Guancheng
;
Li, Cheng
;
Zhu, Yan
;
Zhong, Jianyu
;
Lu, Yan
; et al.
Favorite
|
TC[WOS]:
5
TC[Scopus]:
5
|
Submit date:2018/10/30
Gain Error Calibration
Testing Signal Generation
Sar Adc
Bridge Dac
Low-dropout (Ldo) Regulator
Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area
Journal article
Wang, G. C., Zhu, Y., Chan, C. H., Martins, R. P.. Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 2279-2289.
Authors:
Wang, G. C.
;
Zhu, Y.
;
Chan, C. H.
;
Martins, R. P.
Favorite
|
IF:
2.8
/
2.8
|
Submit date:2022/01/25
Gain error calibration
testing signal generation
SAR ADC
bridge-DAC
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
Journal article
Zhu, Yan, Chan, Chi-Hang, Pan, Seng U., Martins, Rui Paulo. A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(1), 354-363.
Authors:
Zhu, Yan
;
Chan, Chi-Hang
;
Pan, Seng U.
;
Martins, Rui Paulo
Favorite
|
TC[WOS]:
11
TC[Scopus]:
14
IF:
2.8
/
2.8
|
Submit date:2018/10/30
Offset Calibration
Partial Interleaving (Pi)
Pipelined-sar
Stage-gain Error Calibration
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs
Conference paper
Li D., Sin S.-W., Seng-Pan U., Martins R.P.. An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs[C], 2010, 208-211.
Authors:
Li D.
;
Sin S.-W.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
TC[WOS]:
2
TC[Scopus]:
3
|
Submit date:2019/02/11
Capacitor Mismatch
Digital Calibration
Interstage Gain Error
Pipelined Adcs