Residential College | false |
Status | 已發表Published |
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs | |
Li D.2; Sin S.-W.2; Seng-Pan U.2; Martins R.P.1,2 | |
2010-12-01 | |
Conference Name | IEEE Asia Pacific Conference on Circuit and System (APCCAS) |
Source Publication | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS |
Pages | 208-211 |
Conference Date | DEC 06-09, 2010 |
Conference Place | Kuala Lumpur, MALAYSIA |
Abstract | This paper presents a novel digital calibration technique for pipelined ADCs, which compensates both sub-DAC and interstage gain error. The proposed calibration technique is very efficient comparing to other existing calibration techniques, in which only additions and subtractions are employed in this algorithm, no multiplication and division is included. The simplicity of the calibration makes it very easy to be embedded in the mixed signal system design. The power and area overheads due to the calibration circuit are minimized. An example pipelined ADC is designed to demonstrate this calibration technique. Simulation results show that significant improvements can be achieved with the proposed calibration technique. © 2010 IEEE. |
Keyword | Capacitor Mismatch Digital Calibration Interstage Gain Error Pipelined Adcs |
DOI | 10.1109/APCCAS.2010.5774899 |
URL | View the original |
Indexed By | CPCI-S |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000296009300053 |
Scopus ID | 2-s2.0-79959246844 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | INSTITUTE OF MICROELECTRONICS Faculty of Science and Technology DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Affiliation | 1.Instituto Superior Técnico 2.Universidade de Macau |
First Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Li D.,Sin S.-W.,Seng-Pan U.,et al. An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs[C], 2010, 208-211. |
APA | Li D.., Sin S.-W.., Seng-Pan U.., & Martins R.P. (2010). An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 208-211. |
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