Gain-Error-Calibrations for Two-step ADCs:  Optimizations either in Accuracy or Chip Area

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	Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area
	Wang, G. C.; Zhu, Y.; Chan, C. H.; Martins, R. P.
	2018-09-01
Source Publication	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN	1063-8210
Pages	2279-2289
Abstract	This paper presents two calibration schemes to correct the stage-gain error in analog-to-digital converters (ADCs). The two approaches target different scenarios either better calibration accuracy or less digital overhead. First, we optimize the gain calculation scheme in the conventional code-statistic based approach which improves the calibration accuracy. Moreover, we introduce a missing-code-detected (MCD) calibration that replaces the calculation of the gain coefficient by counting and shifting the number of missing-codes in the digital domain, which significantly simplifies the digital implementation. To eliminate the calibration dependence on the input signal we implement a testing-signal-generation (TSG) on-chip. We also compare these calibration schemes with the requirements of the input signal, the calibration accuracy, as well as the hardware overhead based on a mathematical model with behavior simulation. Both concepts were verified in an 80 MS/s 11-bit successive approximation register (SAR) with a bridge digital-to-analog converter (DAC) fabricated in 65nm CMOS.
Keyword	Gain error calibration testing signal generation SAR ADC bridge-DAC
Language	英語English
The Source to Article	PB_Publication
PUB ID	38517
Document Type	Journal article
Collection	DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE
Corresponding Author	Chan, C. H.
Recommended Citation GB/T 7714	Wang, G. C.,Zhu, Y.,Chan, C. H.,et al. Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 2279-2289.
APA	Wang, G. C.., Zhu, Y.., Chan, C. H.., & Martins, R. P. (2018). Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2279-2289.
MLA	Wang, G. C.,et al."Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area".IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018):2279-2289.

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