A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back end. This architecture achieves high speed, while preventing the interleaving spurs. In addition, the design considerations and calibration techniques for gain and offset are also introduced. A histogram stage gain error (HSGE) calibration is implemented to correct the conversion nonlinearities in the digital domain. Measurement results on a 65-nm CMOS prototype show an signal-to-noise distortion ratio (SNDR) of 55.9 dB at dc input and a figure of merit (FoM) of 32 fJ/conversion step at 1.2 V supply.