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A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:15  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
Wideband variable-gain amplifiers based on a pseudo-current-steering gain-tuning technique Journal article
Kong, Lingshan, Chen, Yong, Yu, Haohong, Boon, Chirn Chye, Mak, Pui In, Martins, Rui P.. Wideband variable-gain amplifiers based on a pseudo-current-steering gain-tuning technique[J]. IEEE Access, 2021, 9, 35814-35823.
Authors:  Kong, Lingshan;  Chen, Yong;  Yu, Haohong;  Boon, Chirn Chye;  Mak, Pui In; et al.
Favorite | TC[WOS]:5 TC[Scopus]:7  IF:3.4/3.7 | Submit date：2022/05/13
Active Inductor  Cmos  Data-dependent Jitter (Ddj)  Dual-branch Current Mirror  High-speed Transceiver  Negative CapacitaNce (Nc)  Peak-to-peak Jitter  Pseudo-current Steering  Variable-gain Amplifier (Vga)  Wide-tuning Gain Control  
Wideband variable-gain amplifiers based on a pseudo-current steering gain-tuning technique Journal article
Kong, Lingshan, Chen, Yong, Yu, Haohong, Boon, Chirn Chye, Mak, Pui In, Martins, Rui P.. Wideband variable-gain amplifiers based on a pseudo-current steering gain-tuning technique[J]. IEEE Access, 2021, 9, 35814 -35823.
Authors:  Kong, Lingshan;  Chen, Yong;  Yu, Haohong;  Boon, Chirn Chye;  Mak, Pui In; et al.
Favorite | TC[WOS]:5 TC[Scopus]:7  IF:3.4/3.7 | Submit date：2022/01/25
Cmos  Wide-tuning Gain Control  Variable-gain Amplifier (Vga)  Active Inductor  Data-dependent Jitter (Ddj)  Dual-branch Current Mirror  High-speed Transceiver  Negative CapacitaNce (Nc)  Peak-to-peak Jitter  Pseudo-current Steering  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:22 TC[Scopus]:22  IF:5.2/4.5 | Submit date：2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz Conference paper
Chen, Y., Mak, P. I., Boon, C., Martins, R. P.. A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz[C], 2020.
Authors:  Chen, Y.;  Mak, P. I.;  Boon, C.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
CMOS  output driver  data-dependent jitter  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[Scopus]:16 | Submit date：2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter Journal article
Ge,Xinyi, Chen,Yong, Zhao,Xiaoteng, Mak,Pui In, Martins,Rui P.. Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10), 2223-2236.
Authors:  Ge,Xinyi;  Chen,Yong;  Zhao,Xiaoteng;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:20 TC[Scopus]:20  IF:2.8/2.8 | Submit date：2021/03/09
Bang-bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Binary  Fourier Series  Jitter Generation (Jgen)  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Linear Phase Detector  Loop Filter (Lf)  Sinking Area  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui P. Martins. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(9), 3014-3026.
Authors:  Yong Chen;  Pui-In Mak;  Chirn Chye Boon;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:30  IF:5.2/4.5 | Submit date：2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin Journal article
Chen, Y., Mak, P. I., Boon, C.C., Martins, R. P.. A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 3014-3026.
Authors:  Chen, Y.;  Mak, P. I.;  Boon, C.C.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bandwidth (BW)  cross-quadrature clocking  data- dependent jitter (DDJ)  duobinary  multi-level signaling  CMOS  multiplexer (MUX)  figure-of-merit (FOM)  timing margin  latch  D-type flip-flop (DFF)  selector  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
Balachandran, Arya, Chen, Yong, Choi, Pilsoon, Boon, Chirn Chye. 0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss[J]. ELECTRONICS LETTERS, 2018, 54(2).
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:0.7/0.9 | Submit date：2018/10/30
Equalisers  Circuit Feedback  Analogue Circuits  Random Sequences  Binary Sequences  Cmos Analogue Integrated Circuits  Inductorless Analogue Equaliser  Low-frequency Equalisation Compensation  Lfeq  Low-frequency Channel Loss  Active Feedback Topology  Negative Capacitance Circuit  Data Jitter  Pseudorandom Binary Sequence  Cmos Technology  Loss 15 Db  Bit Rate 13 gBit  s  Size 65 Nm  Voltage 1  2 v