| Residential College | false |
| Status | 已發表Published |
| Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter | |
Ge,Xinyi1; Chen,Yong1  ; Zhao,Xiaoteng1; Mak,Pui In1,2; Martins,Rui P.1,2,3
| |
| 2019-10-01 | |
| Source Publication | IEEE Transactions on Very Large Scale Integration (VLSI) Systems
 |
| ISSN | 1063-8210 |
| Volume | 27Issue:10Pages:2223-2236 |
| Abstract | This paper provides an in-depth analysis of the third-order bang-bang clock and data recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the jitter transfer function (JTF), the jitter tolerance (JTOL), and the jitter generation (JGEN). By formulating the time-domain waveforms, we introduce a characterizing method and also derive the closed-form equations and their simplified versions under specific conditions, which are related with the second-order loop filter (LF). Our framework is consistent with the conclusions of the prior works. Also, we discuss through the time-domain behavior, the sinking area of the JTOL and other specific phenomenon appearing in the third-order BBCDR loop. We verify all above prediction by system-level simulations with the MATLAB/simulink model. |
| Keyword | Bang-bang Clock And Data Recovery (Bbcdr) Bang-bang Phase Detector (Bbpd) Binary Fourier Series Jitter Generation (Jgen) Jitter Tolerance (Jtol) Jitter Transfer Function (Jtf) Linear Phase Detector Loop Filter (Lf) Sinking Area |
| DOI | 10.1109/TVLSI.2019.2915769 |
| URL | View the original |
| Indexed By | SCIE |
| Language | 英語English |
| WOS Research Area | Computer Science ; Engineering |
| WOS Subject | Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic |
| WOS ID | WOS:000489728200001 |
| Scopus ID | 2-s2.0-85077706545 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Journal article |
| Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS |
| Corresponding Author | Chen,Yong |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,999078,Macao 2.Department of Electrical and Computer Engineering,Faculty of Science and Technology,University of Macau,999078,Macao 3.Instituto Superior T cnico,Universidade de Lisboa,Lisbon,1049-001,Portugal |
| First Author Affilication | University of Macau |
| Corresponding Author Affilication | University of Macau |
| Recommended Citation GB/T 7714 | Ge,Xinyi,Chen,Yong,Zhao,Xiaoteng,et al. Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10), 2223-2236. |
| APA | Ge,Xinyi., Chen,Yong., Zhao,Xiaoteng., Mak,Pui In., & Martins,Rui P. (2019). Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(10), 2223-2236. |
| MLA | Ge,Xinyi,et al."Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter".IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27.10(2019):2223-2236. |
| Files in This Item: | There are no files associated with this item. | |||||
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment