English | 繁體

Search in the results

UM

Browse/Search Results:  1-9 of 9 Help

Selected(0)Clear Items/Page:    Sort:
A 16-MHz Crystal Oscillator With 17.5-μs Start-Up Time Under 104-ppm-ΔF Injection Using Automatic Phase-Error Correction Journal article
Wang, Zixuan, Wang, Xin, Lei, Ka Meng, Zhang, Wenjing, Yin, Yunjin, Xu, Tailong, Cai, Zhikuang, Guo, Yufeng, Mak, Pui-In. A 16-MHz Crystal Oscillator With 17.5-μs Start-Up Time Under 104-ppm-ΔF Injection Using Automatic Phase-Error Correction[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59(11), 3780-3790.
Authors:  Wang, Zixuan;  Wang, Xin;  Lei, Ka Meng;  Zhang, Wenjing;  Yin, Yunjin; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/05/16
Automatic Phase-error Correction (Apec)  Crystal Oscillator (Xo)  Fast Start-up  Injection-frequency-mismatch Tolerance  Single-ended Energy Injection  
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment Journal article
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/10/10
Fast Locking  Frequency Synthesis  Frequency-locked Loop (Fll)  Low Jitter  Millimeter-wave (Mm-wave)  Phase-locked Loop (Pll)  Reference (Ref.) Spur  Sub-sampling Phase Detector (Sspd)  Voltage-controlled Oscillator (Vco)  
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrmsJitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment Conference paper
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. 10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrmsJitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment[C]:IEEE, 2024, 204-206.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[Scopus]:4 | Submit date：2024/05/16
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS Conference paper
Yang, Jian, Xu, Tailong, Meng, Xi, Li, Zhenghao, Yin, Jun, Mak, Pui In, Martins, Rui P., Pan, Quan. A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Yang, Jian;  Xu, Tailong;  Meng, Xi;  Li, Zhenghao;  Yin, Jun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up Journal article
Zhang, Zehao, Yang, Shiheng, Liu, Yueduo, Zhu, Zihao, Lin, Jiahui, Bao, Rongxin, Xu, Tailong, Yang, Zhizhan, Zhang, Mingkang, Liu, Jiaxin, Zhou, Xiong, Yin, Jun, Mak, Pui In, Li, Qiang. On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 26-30.
Authors:  Zhang, Zehao;  Yang, Shiheng;  Liu, Yueduo;  Zhu, Zihao;  Lin, Jiahui; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2023/01/30
Bluetooth Low-energy (Ble)  Crystal Oscillator (Xo)  Dc Settling  Duty Cycling  Energy Harvesting  Energy Injection  Initial Motional Current  Internet Of Things (Iot)  Low Power  Startup  
A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction Journal article
Xu, Tailong, Zhong, Shenke, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4774-4786.
Authors:  Xu, Tailong;  Zhong, Shenke;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2023/01/30
Gain-boosting  Low Jitter  Low Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Reference-sampling Phase Detector (Rspd)  Sampling Phase Detector (Spd)  Sub-sampling Phase Detector (Sspd)  Switched-capacitor Voltage Multiplier  
A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108 - 3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2022/01/25
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui In, Li, Qiang, Martins, Rui P.. A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In; et al.
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power  
A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2022/08/19
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power