The settling time of a frequency synthesizer plays a crucial role in determining the dynamic performance of modern wireless and wireline systems which employ power gating and dynamic voltage frequency scaling techniques to reduce power dissipation. The all-digital phase-locked loop (ADPLL), with its digital loop filter (LF), emerges as a superior alternative to the analog PLL since its swift convergence speed and compatibility with digital algorithms. The counter-based ADPLL [1], depicted in Fig. 1 (top-left), can accelerate the locking speed by configuring the digital loop filter in the type-I mode to search the coarse-band switched capacitor control word rapidly. However, a phase offset exists between the REF and D/V clocks after the type-I loop settles, which prolongs the locking time when the loop filter is switched back to the type-II mode for phase locking. To address this limitation, the type-II digital PLL employs frequency and phase locking loop techniques, such as frequency aid [2], [3], tuning word estimation [4], gearshift, and fast-Fourier transform techniques [5], [6], to accelerate the settling process. However, these approaches require a digital loop filter with flexible programmability. Thus, the fast-locking techniques developed for digital PLLs cannot be directly mitigated to the low-jitter type-II sampling PLL [7] using a high-gain but narrow-capture-range sampling phase detector (PD) and a limited programmable analog loop filter. The typical long-time frequency locking behavior is depicted in Fig. 1 (top-right). Even after achieving frequency lock, the out-of-capture range in the phase locking process still results in a long iteration time, as shown by the dashed line in Fig. 1 (bottom-right).