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PISA 研究結果與未來發展/PISA 2018 Findings and Future Development (2020年1-7月期間巡迴到校講解) Presentation
报告日期: 2020-07-23
Authors:  Cheung, K. C.;  Sit, P. S.;  Ieong, M. K.;  Ho, S. P.;  Mak, S. K.; et al.
Favorite |  | Submit date：2022/06/08
A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios Journal article
Un, K. F., Qi, G., Yin, J., Yang, S., Yu, S., Ieong, C. -I., Mak, P. I., Martins, R. P.. A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 3307-3316.
Authors:  Un, K. F.;  Qi, G.;  Yin, J.;  Yang, S.;  Yu, S.; et al.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
digital phase-locked loop (DPLL)  bang-bang  digital-to-time converter (DTC)  gain calibration  voltage-controlled oscillator (VCO)  ring VCO  ultra-low-power (ULP)  ultra-fast settling  
A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures Journal article
Ieong, C. I., Li, M., Law, M. K., Mak, P. I., Vai, M. I., Martins, R. P.. A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017, 1307-1319.
Authors:  Ieong, C. I.;  Li, M.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.; et al.
Favorite | TC[WOS]:25 TC[Scopus]:28  IF:2.8/2.8 | Submit date：2022/01/24
Adaptive Temporal Decimation (Atd)  Data Compression Processor  Electrocardiogram (Ecg)  Near-threshold Digital Logics  Wavelet Transform (Wt)  Wavelet Shrinkage (Ws)  
Practicing digital science assessment in CloudClassroom: A trial study in a Macao school Conference paper
Sit, P. S., Chan, K. L., Mak, S. K., Cheung, K. C., Ieong, M. K., Fong, I. F.. Practicing digital science assessment in CloudClassroom: A trial study in a Macao school[C], 2016.
Authors:  Sit, P. S.;  Chan, K. L.;  Mak, S. K.;  Cheung, K. C.;  Ieong, M. K.; et al.
Favorite |  | Submit date：2022/07/23
Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques Conference paper
Li, M., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., Martins, R. P.. Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques[C], 2016.
Authors:  Li, M.;  Ieong, C. I.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.; et al.
Favorite |  | Submit date：2022/01/24
Sub-threshold Logic  Unbalanced Pull-up/down Network  Logical Effort  Inverse-Narrow-Width Effect  
Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques Journal article
Li, M., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., Martins, R. P.. Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques[J]. IEEE Transactions on Very large scale integration systems, 2015, 3119-3123.
Authors:  Li, M.;  Ieong, C. I.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.; et al.
Favorite |   IF:2.8/2.8 | Submit date：2022/01/24
CMOS  Electrocardiography (ECG)  device sizing  finite impulse response (FIR) filter  inverse-narrow-width (INW)  logical effort  process-voltage-temperature (PVT) variations  sub-threshold standard logic library  ultra-low-energy  ultra-low-voltage  
School report for the 45 schools participating in the print component of the Macao PISA 2012 Study Report
报告类型: 設計報告 Design Report, , 2013
Authors:  Cheung, K. C.;  Sit, P. S.;  Mak, S. K.;  Ieong, M. K.;  Fong, I. F.; et al.
Favorite |  | Submit date：2022/07/21
School Report for the 45 schools participating in the print component of the Macao PISA 2012 Study Report
2013
Authors:  Cheung, K. C.;  Sit, P. S.;  Mak, S. K.;  Ieong, M. K.;  Fong, I. F.; et al.
Favorite |  | Submit date：2022/06/08
mathematics literacy  science literacy  reading literacy  PISA  Macao  
A 0.83-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35-µm CMOS Journal article
Ieong, C.I., Mak, P. I., Lam, C.P., Dong, C., Vai, M. I., Mak, P. U., Pun, S. H., Wan, F., Martins, R. P.. A 0.83-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35-µm CMOS[J]. IEEE Transactions on Biomedical Circuits and Systems, 2012, 586-595.
Authors:  Ieong, C.I.;  Mak, P. I.;  Lam, C.P.;  Dong, C.;  Vai, M. I.; et al.
Favorite |   IF:3.8/4.8 | Submit date：2022/01/24
QRS detection  quadratic spline wavelet transform  wavelet transform  wearable electrocardiograph (ECG) device  wireless ECG monitoring  
School report for 45 schools participating in the digital component of the Macao PISA 2009 Study Report
2011
Authors:  Cheung, K. C.;  Sit, P. S.;  Mak, S. K.;  Ieong, M. K.;  Fong, I. F.; et al.
Favorite |  | Submit date：2022/06/08
PISA 2009  digital assessment  Macao