| Status | 已發表Published |
| Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques | |
Li, M. ; Ieong, C. I.; Law, M. K.; Mak, P. I.; Vai, M. I. ; Pun, S. H.; Martins, R. P.
| |
| 2016 | |
| Source Publication | 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
 |
| Abstract | This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-µm CMOS technology, while one of them achieved the minimum energy/tap (0.0234 pJ) and 0.365 Figure-of-Merit (FoM) at 100 kHz, 0.31 V. |
| Keyword | Sub-threshold Logic Unbalanced Pull-up/down Network Logical Effort Inverse-Narrow-Width Effect |
| URL | View the original |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 19457 |
| Document Type | Conference paper |
| Collection | Institute of Chinese Medical Sciences |
| Recommended Citation GB/T 7714 | Li, M.,Ieong, C. I.,Law, M. K.,et al. Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques[C], 2016. |
| APA | Li, M.., Ieong, C. I.., Law, M. K.., Mak, P. I.., Vai, M. I.., Pun, S. H.., & Martins, R. P. (2016). Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques. 21st Asia and South Pacific Design Automation Conference (ASP-DAC). |
| Files in This Item: | There are no files associated with this item. | |||||
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment