Residential College | false |
Status | 已發表Published |
A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures | |
Ieong, C. I.; Li, M.; Law, M. K.; Mak, P. I.; Vai, M. I.; Martins, R. P. | |
2017-04-01 | |
Source Publication | IEEE Transactions on Very Large Scale Integration Systems |
ISSN | 1063-8210 |
Pages | 1307-1319 |
Abstract | This paper presents a real-time ECG data compression processor with improved energy efficiency while maintaining high accuracy and real-time operation. Wavelet shrinkage (WS) is exploited to filter the noise and achieve sparse ECG signal representation. Adaptive temporal decimation (ATD) is proposed to achieve configurable processing to adaptively reduce the data amount and computational activities for further power reduction. Modified Huffman and run-length wavelet source coding (MHRLC) is also designed to represent wavelet coefficients with optimized average code length and reduced memory requirement. Fabricated in 0.18-µm CMOS, the ECG processor is implemented with customized near-threshold digital logics for minimum energy operation. The prototype was fully validated with the MIT-BIH Arrhythmia database. With a power consumption of 147-to-375 nW at 0.45 V, the proposed ECG processor exhibits a wide compression ratio (CR) ranging from 2.89 to 26.91, corresponding to a percentage-RMS-distortion (PRD) from 0 to 3.11%. |
Keyword | Adaptive Temporal Decimation (Atd) Data Compression Processor Electrocardiogram (Ecg) Near-threshold Digital Logics Wavelet Transform (Wt) Wavelet Shrinkage (Ws) |
DOI | 10.1109/TVLSI.2016.2638826 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Computer Science ; Engineering |
WOS Subject | Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic |
WOS ID | WOS:000398858800011 |
The Source to Article | PB_Publication |
Scopus ID | 2-s2.0-85008481754 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Law, M. K. |
Recommended Citation GB/T 7714 | Ieong, C. I.,Li, M.,Law, M. K.,et al. A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017, 1307-1319. |
APA | Ieong, C. I.., Li, M.., Law, M. K.., Mak, P. I.., Vai, M. I.., & Martins, R. P. (2017). A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures. IEEE Transactions on Very Large Scale Integration Systems, 1307-1319. |
MLA | Ieong, C. I.,et al."A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures".IEEE Transactions on Very Large Scale Integration Systems (2017):1307-1319. |
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