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A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures
Ieong, C. I.; Li, M.; Law, M. K.; Mak, P. I.; Vai, M. I.; Martins, R. P.
2017-04-01
Source PublicationIEEE Transactions on Very Large Scale Integration Systems
ISSN1063-8210
Pages1307-1319
Abstract

This paper presents a real-time ECG data compression processor with improved energy efficiency while maintaining high accuracy and real-time operation. Wavelet shrinkage (WS) is exploited to filter the noise and achieve sparse ECG signal representation. Adaptive temporal decimation (ATD) is proposed to achieve configurable processing to adaptively reduce the data amount and computational activities for further power reduction. Modified Huffman and run-length wavelet source coding (MHRLC) is also designed to represent wavelet coefficients with optimized average code length and reduced memory requirement. Fabricated in 0.18-µm CMOS, the ECG processor is implemented with customized near-threshold digital logics for minimum energy operation. The prototype was fully validated with the MIT-BIH Arrhythmia database. With a power consumption of 147-to-375 nW at 0.45 V, the proposed ECG processor exhibits a wide compression ratio (CR) ranging from 2.89 to 26.91, corresponding to a percentage-RMS-distortion (PRD) from 0 to 3.11%.

KeywordAdaptive Temporal Decimation (Atd) Data Compression Processor Electrocardiogram (Ecg) Near-threshold Digital Logics Wavelet Transform (Wt) Wavelet Shrinkage (Ws)
DOI10.1109/TVLSI.2016.2638826
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000398858800011
The Source to ArticlePB_Publication
Scopus ID2-s2.0-85008481754
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Citation statistics
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorLaw, M. K.
Recommended Citation
GB/T 7714
Ieong, C. I.,Li, M.,Law, M. K.,et al. A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017, 1307-1319.
APA Ieong, C. I.., Li, M.., Law, M. K.., Mak, P. I.., Vai, M. I.., & Martins, R. P. (2017). A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures. IEEE Transactions on Very Large Scale Integration Systems, 1307-1319.
MLA Ieong, C. I.,et al."A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures".IEEE Transactions on Very Large Scale Integration Systems (2017):1307-1319.
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