Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques

UM > Faculty of Science and Technology > DEPARTMENT OF MATHEMATICS

Residential College	false
Status	已發表Published
	Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques
	Li, M.; Ieong, C. I.; Law, M. K.; Mak, P. I.; Vai, M. I.; Pun, S. H.; Martins, R. P.
	2015-12-01
Source Publication	IEEE Transactions on Very large scale integration systems
ISSN	1063-8210
Pages	3119-3123
Abstract	Ultra-low-energy biomedical applications have urged the development of a sub-threshold VLSI logic family in standard CMOS. This Brief proposes an unbalanced pull-up/down network, together with an inverse-narrow-width technique, to improve the operating speed of the individual logic cell. Effective logical efforts save both power and die area in the process of device sizing and topology optimization. Three experimental 14-tap 8-bit finite impulse response (FIR) filters optimized for ultra-low-voltage operation were fabricated in 0.18-μm CMOS. Measurements show that the optimized 0.45-V and 0.6-V libraries achieve minimum energy operations at 100 kHz, with a Figure-of-Merit (FoM) of 0.365 (at 0.31 V) and 0.4632 (at 0.39 V), respectively. They correspond to 35.96% and 18.74% improvements, and the overall performances are well comparable with the state-of-the-art.
Keyword	CMOS Electrocardiography (ECG) device sizing finite impulse response (FIR) filter inverse-narrow-width (INW) logical effort process-voltage-temperature (PVT) variations sub-threshold standard logic library ultra-low-energy ultra-low-voltage
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	14915
Document Type	Journal article
Collection	DEPARTMENT OF MATHEMATICS
Corresponding Author	Law, M. K.
Recommended Citation GB/T 7714	Li, M.,Ieong, C. I.,Law, M. K.,et al. Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques[J]. IEEE Transactions on Very large scale integration systems, 2015, 3119-3123.
APA	Li, M.., Ieong, C. I.., Law, M. K.., Mak, P. I.., Vai, M. I.., Pun, S. H.., & Martins, R. P. (2015). Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques. IEEE Transactions on Very large scale integration systems, 3119-3123.
MLA	Li, M.,et al."Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques".IEEE Transactions on Very large scale integration systems (2015):3119-3123.

Files in This Item:
There are no files associated with this item.

If you have any objections to this item, please fill out the form below and the administrator will contact you as soon as possible.
Content:
Email：	*
Affiliation No.
Verification Code:	Refresh

Any comments and suggestions are welcomed.
Title:	*
Content:
Email：	*
Verification Code:	Refresh