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E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1 Journal article
Duan, Chunyan, Li, Yue, Zhi, Haoyu, Tian, Yao, Huang, Zhengyun, Chen, Suping, Zhang, Yang, Liu, Qing, Zhou, Liang, Jiang, Xiaogang, Ullah, Kifayat, Guo, Qing, Liu, Zhaohui, Xu, Ying, Han, Junhai, Hou, Jiajie, O’Connor, Darran P., Xu, Guo qiang. E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1[J]. ACTA PHARMACOLOGICA SINICA, 2024, 45, 1793-1808.
Authors:  Duan, Chunyan;  Li, Yue;  Zhi, Haoyu;  Tian, Yao;  Huang, Zhengyun; et al.
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:6.9/7.6 | Submit date：2024/06/05
Bmal1  Circadian Rhythm  Proteomics  Transcriptional Activity  Ubiquitination  Ubr5  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:IEEE, 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
Zhang, Ran, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Xu, Dengke, Zhao, Weibing, Martins, R. P., Maloberti, Franco, Sin, Sai Weng. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C], 2024.
Authors:  Zhang, Ran;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang;  Xu, Dengke; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/08/05
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering Conference paper
Li, Ke, Congzhou, Xianyu, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Li, Ke;  Congzhou, Xianyu;  Qi, Liang;  Guo, Mingqiang;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
Correction to: E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1 (Acta Pharmacologica Sinica, (2024), 10.1038/s41401-024-01290-z) Other
2024-01-01
Authors:  Duan, Chun Yan;  Li, Yue;  Zhi, Hao Yu;  Tian, Yao;  Huang, Zheng Yun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/07/04
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:  Guo Mingqiang;  Qi Liang;  Zhao Weibing;  Xiao Gangjun;  Rui P. Martins; et al.
Adobe PDF | Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2023/08/21
Analog-to-digital Converter (Adc)  Successive Approximation Register (Sar)  Power-delay-optimized  Unbalanced N/p-mos Sizing Buffers  Monotonic Switching  
8.4 An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz FoMT Conference paper
Hao Guo, Yong Chen, Yunbo Huang, Pui In Mak, Rui P. Martins. 8.4 An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz FoMT[C]:Institute of Electrical and Electronics Engineers Inc., 2023, 152-154.
Authors:  Hao Guo;  Yong Chen;  Yunbo Huang;  Pui In Mak;  Rui P. Martins
Favorite | TC[Scopus]:8 | Submit date：2023/08/03
Power-Efficient RF and mm-Wave VCOs/PLL Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:51-89
Authors:  Hao Guo;  Zunsong Yang;  Chee Cheow Lim;  Harikrishnan Ramiah;  Yatao Peng; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Harmonic Tuning  Inverse Class-f  Jitter  Millimeter Wave (mm-Wave)  Mode-switching  Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Subsampling  Voltage-controlled Oscillator (Vco)  
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward Journal article
Zhao,Shulin, Guo,Mingqiang, Qi,Liang, Xu,Dengke, Wang,Guoxing, Martins,Rui P., Sin,Sai Weng. A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10), 2722-2732.
Authors:  Zhao,Shulin;  Guo,Mingqiang;  Qi,Liang;  Xu,Dengke;  Wang,Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2023/08/03
Error-feedforward (Ff)  Midway Error-feedback (Fb)  Noise Transfer Function (Ntf) Peaking  Offset Reduction  Redundancy  Time-interleaving Noise-shaping Successive Approximation Register (Ns-sar)  
A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction Conference paper
Zhao, Shulin, Guo, Mingqiang, Sin, Sai Weng, Qi, Liang, Xu, Dengke, Wang, Guoxing, Martins, Rui P.. A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction[C]:IEEE, 2022.
Authors:  Zhao, Shulin;  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke; et al.
Adobe PDF | Favorite | TC[Scopus]:1 | Submit date：2023/03/06