| Residential College | false |
| Status | 已發表Published |
| A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction | |
Zhao, Shulin1 ; Guo, Mingqiang1  ; Sin, Sai Weng1,2; Qi, Liang3; Xu, Dengke4; Wang, Guoxing3; Martins, Rui P.1
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| 2022-12 | |
| Conference Name | 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| Source Publication | 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
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| Conference Date | 06-09 November 2022 |
| Conference Place | Taipei |
| Country | Taiwan |
| Publisher | IEEE |
| Abstract | The noise-shaping SAR (NS-SAR) combines the merits of the Delta - Sigma and the SAR ADCs, transforming it into an emerging ADC architecture to pull off high resolution and high power efficiency. However, the existing single-channel NS-SAR obtaining SNDR gt 70 dB always suffers from bandwidth (BW) limitation <10 MHz due to the following reasons [1]: First, the settling time in the SAR's DAC increases significantly to meet high-resolution requirements with the large size of the CDAC. Besides, implementing a sharp noise transfer function (NTF) always involves residue amplification to compensate for the signal attenuation, which occupies a portion of time and leaves less time for SAR conversion. |
| DOI | 10.1109/A-SSCC56115.2022.9980691 |
| URL | View the original |
| Indexed By | CPCI-S ; EI |
| Language | 英語English |
| Scopus ID | 2-s2.0-85146570975 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Guo, Mingqiang; Sin, Sai Weng |
| Affiliation | 1.University of Macau, Macao 2.Zhuhai Um Science and Technology Research Institute, 3.Shanghai Jiao Tong University, Amicro Semiconductor Co., Ltd, China 4.University of Lisboa, Portugal |
| First Author Affilication | University of Macau |
| Corresponding Author Affilication | University of Macau |
| Recommended Citation GB/T 7714 | Zhao, Shulin,Guo, Mingqiang,Sin, Sai Weng,et al. A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction[C]:IEEE, 2022. |
| APA | Zhao, Shulin., Guo, Mingqiang., Sin, Sai Weng., Qi, Liang., Xu, Dengke., Wang, Guoxing., & Martins, Rui P. (2022). A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction. 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings. |
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| A_3.07mW_30MHz-BW_73（624KB） | 会议论文 | 开放获取 | CC BY-NC-SA | View Download | ||
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