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A 0.6V 8b 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS Conference paper
Wu, W.L., Zhu, Y, Ding, L., Chan, C.H., Chio, U.F., Sin, S. W., U, S.P., Martins, R. P.. A 0.6V 8b 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS[C], US:IEEE, 2013, 2239-2242.
Authors:  Wu, W.L.;  Zhu, Y;  Ding, L.;  Chan, C.H.;  Chio, U.F.; et al.
Favorite | TC[WOS]:10 TC[Scopus]:10 | Submit date：2022/01/24
Analog-to-digital Converters  Adc  
A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC Journal article
Wei, W.G., Chan, C.H., Chio, U.F., Sin, S. W., U, S.P., Martins, R. P., Maloberti, F. A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC[J]. IEEE Journal of Solid-State Circuits, 2012, 2763-2772.
Authors:  Wei, W.G.;  Chan, C.H.;  Chio, U.F.;  Sin, S. W.;  U, S.P.; et al.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Sar  Resistive Dac  
A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS Conference paper
Wei, H.G., Chan, C.H., Chio, U.F., Sin, S. W., U, S.P., Martins, R. P., Maloberti, F. A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS[C], San Francisco:IEEE, 2011, 188-189.
Authors:  Wei, H.G.;  Chan, C.H.;  Chio, U.F.;  Sin, S. W.;  U, S.P.; et al.
Favorite |  | Submit date：2022/01/25
Analog-to-Digital Converter  SAR ADC  
A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS Journal article
Zhu, Y., Chan, C.H., Chio, U.F., Sin, S. W., U, S.P., Martins, R. P., Maloberti, F.. A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2010, 1111-1121.
Authors:  Zhu, Y.;  Chan, C.H.;  Chio, U.F.;  Sin, S. W.;  U, S.P.; et al.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Adc  Sar  Charge-recovery  Switched Technique  
A process-and temperature-insensitive current-controlled delay generator for sampled-data systems Conference paper
Wei, H. G., Chio, U.F., Zhu, Y., U, S.P., Martins, R. P.. A process-and temperature-insensitive current-controlled delay generator for sampled-data systems[C], 2008.
Authors:  Wei, H. G.;  Chio, U.F.;  Zhu, Y.;  U, S.P.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
Process & temperature-insensitive  Delay generator  Current-controlled