| Residential College | false |
| Status | 已發表Published |
| A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC | |
Wei, W.G. ; Chan, C.H.; Chio, U.F.; Sin, S. W.; U, S.P.; Martins, R. P.; Maloberti, F
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| 2012-11-01 | |
| Source Publication | IEEE Journal of Solid-State Circuits
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| ISSN | 0018-9200 |
| Pages | 2763-2772 |
| Abstract | An 8-bit 400MS/s 2-bit per cycle (2b/C) Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is fabricated in 65nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low-power and compact area leading to SNDR of 44.5dB and SFDR of 54.0dB, at 400MS/s with 1.9MHz input. The measured FOM is 73fJ/conversion-step at 400MS/s from 1.2V supply and 42fJ/conversion-step at 250MS/s from 1V supply. The active area with the digital calibration is 0.028mm2. |
| Keyword | Analog-to-digital Converter Sar Resistive Dac |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 8929 |
| Document Type | Journal article |
| Collection | DEPARTMENT OF PSYCHOLOGY |
| Recommended Citation GB/T 7714 | Wei, W.G.,Chan, C.H.,Chio, U.F.,et al. A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC[J]. IEEE Journal of Solid-State Circuits, 2012, 2763-2772. |
| APA | Wei, W.G.., Chan, C.H.., Chio, U.F.., Sin, S. W.., U, S.P.., Martins, R. P.., & Maloberti, F (2012). A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC. IEEE Journal of Solid-State Circuits, 2763-2772. |
| MLA | Wei, W.G.,et al."A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC".IEEE Journal of Solid-State Circuits (2012):2763-2772. |
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