A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS

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	A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS
	Wei, H.G.; Chan, C.H.; Chio, U.F.; Sin, S. W.; U, S.P.; Martins, R. P.; Maloberti, F
	2011-02-24
Source Publication	IEEE International Solid-State Circuit Conference (ISSCC)
Pages	188-189
Publication Place	San Francisco
Publisher	IEEE
Abstract	The successive-approximation (SA) algorithm is traditionally used for lowbandwidth applications because it requires n clock cycles or more to obtain nbit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions [1]. This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Key features of the architecture are a resistive DAC and a 2b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a silicon area of 0.024 mm2.
Keyword	Analog-to-Digital Converter SAR ADC
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	8952
Document Type	Conference paper
Collection	DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE
Recommended Citation GB/T 7714	Wei, H.G.,Chan, C.H.,Chio, U.F.,et al. A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS[C], San Francisco:IEEE, 2011, 188-189.
APA	Wei, H.G.., Chan, C.H.., Chio, U.F.., Sin, S. W.., U, S.P.., Martins, R. P.., & Maloberti, F (2011). A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS. IEEE International Solid-State Circuit Conference (ISSCC), 188-189.

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