| Residential College | false |
| Status | 已發表Published |
| A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS | |
Zhu, Y. ; Chan, C.H.; Chio, U.F.; Sin, S. W.; U, S.P.; Martins, R. P.; Maloberti, F.
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| 2010-06-01 | |
| Source Publication | IEEE Journal of Solid-State Circuits
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| ISSN | 0018-9200 |
| Pages | 1111-1121 |
| Abstract | A 1.2 V 10-bit 100MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes reset time for the preamplifier to improve the conversion speed. Measurement results on a 90nm CMOS prototype operated at 1.2V supply show 3mW total power consumption with a peak SNDR of 56.6dB and a FOM of 77fJ/conv-step. |
| Keyword | Analog-to-digital Converter Adc Sar Charge-recovery Switched Technique |
| URL | View the original |
| Language | 英語English |
| The Source to Article | PB_Publication |
| Document Type | Journal article |
| Collection | University of Macau |
| Recommended Citation GB/T 7714 | Zhu, Y.,Chan, C.H.,Chio, U.F.,et al. A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2010, 1111-1121. |
| APA | Zhu, Y.., Chan, C.H.., Chio, U.F.., Sin, S. W.., U, S.P.., Martins, R. P.., & Maloberti, F. (2010). A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS. IEEE Journal of Solid-State Circuits, 1111-1121. |
| MLA | Zhu, Y.,et al."A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS".IEEE Journal of Solid-State Circuits (2010):1111-1121. |
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