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Dual-Working-Modes-Based Common Grounded Nonisolated DC-DC Converter With a Wide Voltage-Gain Range for Photovoltaic Applications Journal article
Li, Zou, Liu, Junfeng, Yang, Ningrui, Ying, Gengning, Zeng, Jun. Dual-Working-Modes-Based Common Grounded Nonisolated DC-DC Converter With a Wide Voltage-Gain Range for Photovoltaic Applications[J]. IEEE Transactions on Energy Conversion, 2024, 39(2), 1088-1102.
Authors:  Li, Zou;  Liu, Junfeng;  Yang, Ningrui;  Ying, Gengning;  Zeng, Jun
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:5.0/5.1 | Submit date：2024/02/22
Dc–dc  Dual Working Modes  Low Current Ripple  Photovoltaic Applications  Wide Voltage-gain Range  
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:7 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:5 TC[Scopus]:10  IF:2.8/2.8 | Submit date：2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii  
A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction Journal article
Xu, Tailong, Zhong, Shenke, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4774-4786.
Authors:  Xu, Tailong;  Zhong, Shenke;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:9 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/01/30
Gain-boosting  Low Jitter  Low Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Reference-sampling Phase Detector (Rspd)  Sampling Phase Detector (Spd)  Sub-sampling Phase Detector (Sspd)  Switched-capacitor Voltage Multiplier  
Effects of Parasitic Resistances on Π-Source Impedance Network Journal article
Ieong, Chi Fong, Leong, Chio Hong, Kong, Xiangfei, Wong, Chi Kong, Lam, Chi Seng. Effects of Parasitic Resistances on Π-Source Impedance Network[J]. IEEE Access, 2021, 9, 76403-76412.
Authors:  Ieong, Chi Fong;  Leong, Chio Hong;  Kong, Xiangfei;  Wong, Chi Kong;  Lam, Chi Seng
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:3.4/3.7 | Submit date：2022/05/13
Coupled Inductors  Magnetically Coupled Impedance-source Network  Parasitic Resistances  Voltage Gain  Π-source Impedance-source Network  
Effects of parasitic resistances on Π-source impedance networks Journal article
Ieong, C. F., Leong, C. H., Kong, X., Wong, C. K., Lam, C. S.. Effects of parasitic resistances on Π-source impedance networks[J]. IEEE Access, 2021, 76403-76412.
Authors:  Ieong, C. F.;  Leong, C. H.;  Kong, X.;  Wong, C. K.;  Lam, C. S.
Favorite |   IF:3.4/3.7 | Submit date：2022/08/12
Coupled Inductors  Magnetically Coupled Impedance-source Network  Π-source Impedance-source Network  Parasitic Resistances  Voltage Gain  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), 3753-3763.
Authors:  Xiaofeng Yang;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:8 TC[Scopus]:9  IF:5.2/4.5 | Submit date：2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
Effects of Parasitic Resistances on Magnetically Coupled Impedance-Source Networks Journal article
Kong,Xiangfei, Wong,Chi Kong, Lam,Chi Seng. Effects of Parasitic Resistances on Magnetically Coupled Impedance-Source Networks[J]. IEEE Transactions on Power Electronics, 2020, 35(9), 9171-9183.
Authors:  Kong,Xiangfei;  Wong,Chi Kong;  Lam,Chi Seng
Favorite | TC[WOS]:12 TC[Scopus]:13  IF:6.6/6.9 | Submit date：2021/03/11
Magnetically Coupled Impedance-source Netwo-rks  Parasitic Resistances  Trans-z-source  Voltage Gain  Y-source  Г-source  
A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios Journal article
Un, K. F., Qi, G., Yin, J., Yang, S., Yu, S., Ieong, C. -I., Mak, P. I., Martins, R. P.. A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 3307-3316.
Authors:  Un, K. F.;  Qi, G.;  Yin, J.;  Yang, S.;  Yu, S.; et al.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
digital phase-locked loop (DPLL)  bang-bang  digital-to-time converter (DTC)  gain calibration  voltage-controlled oscillator (VCO)  ring VCO  ultra-low-power (ULP)  ultra-fast settling  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
Un,Ka Fai, Qi,Gengzhen, Yin,Jun, Yang,Shiheng, Yu,Shupeng, Ieong,Chio In, Mak,Pui In, Martins,Rui P.. A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3307-3316.
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng; et al.
Favorite | TC[WOS]:11 TC[Scopus]:12  IF:5.2/4.5 | Submit date：2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)