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Effects of Parasitic Resistances on Π-Source Impedance Network
Ieong, Chi Fong1,2,3; Leong, Chio Hong1,2,3; Kong, Xiangfei1,2,3; Wong, Chi Kong3; Lam, Chi Seng1,2,3
2021-05-20
Source PublicationIEEE Access
ISSN2169-3536
Volume9Pages:76403-76412
Abstract

Magnetically coupled impedance-source networks are often connected with voltage source inverter to obtain a higher voltage gain and achieve less shoot-through duty ratio occupation. Among them, Π -source impedance source network was proposed to achieve higher voltage gain, lower current stress, smaller core size, and also smaller circulating current when compared with the conventional Δ -source inverter, but it still faces the problem of the voltage gain reduction caused by the parasitic resistances. The parasitic resistance effect becomes more serious by the high operating current nature of magnetically coupled impedance-source networks. Therefore, in this paper, the effect of parasitic resistances on Π -source impedance network is investigated by modeling the Π -source converter with parasitic resistances consideration. Based on this, the voltage gain is firstly deduced and analyzed. Then, the characteristic of the voltage gain is researched under different shoot-through duty ratios, different winding ratios, and different resistances ratios. Different from the ideal lossless case, the voltage gain increases first and then decreases when the shoot-through duty ratio becomes larger. Finally, the correctness of the deduction and analysis in this paper is verified by corresponding simulation and experimental results.

KeywordCoupled Inductors Magnetically Coupled Impedance-source Network Parasitic Resistances Voltage Gain Π-source Impedance-source Network
DOI10.1109/ACCESS.2021.3082401
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaComputer Science ; Engineering ; Telecommunications
WOS SubjectComputer Science, Information Systems ; Engineering, Electrical & Electronic ; Telecommunications
WOS IDWOS:000673601100001
Scopus ID2-s2.0-85107153501
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionTHE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)
DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE
Corresponding AuthorLam, Chi Seng
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, 999078, Macao
2.Institute of Microelectronics, University of Macau, 999078, Macao
3.Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, 999078, Macao
First Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Corresponding Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Recommended Citation
GB/T 7714
Ieong, Chi Fong,Leong, Chio Hong,Kong, Xiangfei,et al. Effects of Parasitic Resistances on Π-Source Impedance Network[J]. IEEE Access, 2021, 9, 76403-76412.
APA Ieong, Chi Fong., Leong, Chio Hong., Kong, Xiangfei., Wong, Chi Kong., & Lam, Chi Seng (2021). Effects of Parasitic Resistances on Π-Source Impedance Network. IEEE Access, 9, 76403-76412.
MLA Ieong, Chi Fong,et al."Effects of Parasitic Resistances on Π-Source Impedance Network".IEEE Access 9(2021):76403-76412.
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