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A 0.32 × 0.12 mm2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout Journal article
Peng, Yatao, Benserhir, Jad, Castaneda, Mario, Fognini, Andreas, Bruschini, Claudio, Charbon, Edoardo. A 0.32 × 0.12 mm2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout[J]. IEEE Transactions on Microwave Theory and Techniques, 2024, 72(4), 2179-2192.
Authors:  Peng, Yatao;  Benserhir, Jad;  Castaneda, Mario;  Fognini, Andreas;  Bruschini, Claudio; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.1/4.2 | Submit date：2024/05/02
Bicmos  Cryogenic Temperatures  Low-noise Amplifiers  Sige Heterojunction Bipolar Transistor (Hbt)  Superconducting Single-photon Detectors  Timing Jitter  
A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
Guo, M., Mao, J., Sin,SS. W., Wei, H., Martins, R. P.. A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 693-705.
Authors:  Guo, M.;  Mao, J.;  Sin,SS. W.;  Wei, H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Calibration  Timing  Clocks  Impedance  Signal To Noise Ratio  Channel Estimation  Jitter  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui P. Martins. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(9), 3014-3026.
Authors:  Yong Chen;  Pui-In Mak;  Chirn Chye Boon;  Rui P. Martins
Favorite | TC[WOS]:26 TC[Scopus]:29  IF:5.2/4.5 | Submit date：2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin Journal article
Chen, Y., Mak, P. I., Boon, C.C., Martins, R. P.. A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 3014-3026.
Authors:  Chen, Y.;  Mak, P. I.;  Boon, C.C.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bandwidth (BW)  cross-quadrature clocking  data- dependent jitter (DDJ)  duobinary  multi-level signaling  CMOS  multiplexer (MUX)  figure-of-merit (FOM)  timing margin  latch  D-type flip-flop (DFF)  selector  
Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering Book
U Seng Pan, Martins Rui Paulo, Epifanio da Franca Jose de Albuquerque. Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering[M]. US:Springer US, 2006, 250.
Authors:  U Seng Pan;  Martins Rui Paulo;  Epifanio da Franca Jose de Albuquerque
Favorite | TC[Scopus]:0 | Submit date：2019/02/26
Cmos  Cmos Analog Integrated Circuit  Filter  Front-end Filtering  Gain & Offset Compensation  High-frequency  Multirate Signal Processing  Secs  Switched-capacitor  The Kluwer International Series In engIneerIng And Computer  Timing-mismatch And Jitter  Calculus  Consumption  Integrated Circuit  
Spectra analysis of nonuniformly holding signals for time-interleaved systems with timing mismatches Conference paper
Sin S.-W., Martins R.P., U, SP. Spectra analysis of nonuniformly holding signals for time-interleaved systems with timing mismatches[C], 2003, 1298-1301.
Authors:  Sin S.-W.;  Martins R.P.;  U, SP
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/02/11
Signal Analysis  Timing  Signal Processing  Frequency  Clocks  Signal Sampling  Jitter  Silicon Compounds  Closed-form Solution  Error Analysis