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A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[C], 2020, 283-284.
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:7 | Submit date：2021/03/09
Phase Detector  Phase Locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Rms Jitter  
“A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Yang, Z., Chen, Y., Mak, P. I., Martins, R. P.. “A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[C], 2019.
Authors:  Yang, Z.;  Chen, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Ring voltage-controlled oscillator (VCO)  phase locked loop (PLL)  reference spur  RMS jitter  phase detector.  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
Yang, S., Yin, J., Mak, P. I., Martins, R. P.. A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 88-98.
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2022/01/24
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits, 2019, 54(1), 88-98.
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter