| Status | 已發表Published |
| “A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS | |
Yang, Z. ; Chen, Y. ; Mak, P. I.; Martins, R. P.
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| 2019-11-06 | |
| Source Publication | RF Signal Synthesizers
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| Abstract | This paper reports a current-reuse sampling phase detector for a type-I phase-locked loop (PLL) to simultaneously achieve both wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures a jitter of 440 fsRMS, and a spur level of -64 dBc at 3.296 GHz. The die area is 0.003 mm2. |
| Keyword | Ring voltage-controlled oscillator (VCO) phase locked loop (PLL) reference spur RMS jitter phase detector. |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 48676 |
| Document Type | Conference paper |
| Collection | University of Macau |
| Corresponding Author | Chen, Y. |
| Recommended Citation GB/T 7714 | Yang, Z.,Chen, Y.,Mak, P. I.,et al. “A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[C], 2019. |
| APA | Yang, Z.., Chen, Y.., Mak, P. I.., & Martins, R. P. (2019). “A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. RF Signal Synthesizers. |
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