English | 繁體

Search in the results

UM

Browse/Search Results:  1-10 of 10 Help

Selected(0)Clear Items/Page:    Sort:
Point Cloud Compression with Implicit Neural Representations: A Unified Framework Conference paper
Ruan, Hongning, Shao, Yulin, Yang, Qianqian, Zhao, Liang, Niyato, Dusit. Point Cloud Compression with Implicit Neural Representations: A Unified Framework[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 1709-1714.
Authors:  Ruan, Hongning;  Shao, Yulin;  Yang, Qianqian;  Zhao, Liang;  Niyato, Dusit
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/11/05
Point Cloud Compression  Geometry  Learning Systems  Three-dimensional Displays  Quantization (Signal)  Neural Networks  Rate-distortion  Point Cloud Compression  Implicit Neural Representation  Neural Network Compression  
A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration Conference paper
Zhang, Wei, Zhang, Minglei, Zhu, Yan, Martins, R. P., Chan, Chi Hang. A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 28-3.
Authors:  Zhang, Wei;  Zhang, Minglei;  Zhu, Yan;  Martins, R. P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:2 | Submit date：2024/06/05
Application Specific Integrated Circuits  Quantization (Signal)  Prototypes  Linearity  Receivers  Bandwidth  Calibration  
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS Conference paper
Qin, Xinyu, Jin, Yichen, Wang, Guoxing, Sin, Sai Weng, Ortmanns, Maurits, Lian, Yong, Qi, Liang. A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Qin, Xinyu;  Jin, Yichen;  Wang, Guoxing;  Sin, Sai Weng;  Ortmanns, Maurits; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2024/06/05
Multi-stage Noise Shaping  Application Specific Integrated Circuits  Quantization (Signal)  Cmos Integrated Circuits  
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs Conference paper
Chan, Chi Hana, Zhang, Minglei, Cao, Yuefena, Zhao, Honazhi, Martins, Rui P., Zhu, Yan. The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 28-1.
Authors:  Chan, Chi Hana;  Zhang, Minglei;  Cao, Yuefena;  Zhao, Honazhi;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
Technological Innovation  Quantization (Signal)  Power Demand  Energy Resolution  Reliability Engineering  Energy Efficiency  Trajectory  Time-domain Analysis  Task Analysis  Signal Resolution  
A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan Gaofeng, Qin Xinyu, Liu Yan, Guo Mingqiang, Sin Sai-Weng, Wang Guoxing, Lian Yong, Qi Liang. A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023.
Authors:  Tan Gaofeng;  Qin Xinyu;  Liu Yan;  Guo Mingqiang;  Sin Sai-Weng; et al.
Adobe PDF | Favorite |   IF:5.2/4.5 | Submit date：2023/08/22
Multi-stage Noise Shaping , Topology , Delays , Robustness , Quantization (Signal) , Calibration , Thermal Stability  
A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS Journal article
Xiangyu Mao, Yan Lu, Rui P. Martins. A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(11), 4443-4452.
Authors:  Xiangyu Mao;  Yan Lu;  Rui P. Martins
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2022/09/09
Calibration  Codes  Digital  Distributed Power Delivery  Dynamic Voltage And Frequency Scaling (Dvfs)  Fully-integrated Voltage Regulator (Fivr)  Hybrid Control  Hybrid Power Systems  Low-dropout Regulator (Ldo)  Power Transistors  Quantization (Signal)  Thermometers  Voltage Control  
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
Zhang, Qihui, Ning, Ning, Zhang, Zhong, Li, Jing, Wu, Kejun, Chen, Yong, Yu, Qi. A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration[J]. IEEE Journal of Solid-State Circuits, 2022, 57(7), 2181-2195.
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun; et al.
Favorite | TC[WOS]:26 TC[Scopus]:29  IF:4.6/5.6 | Submit date：2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, Kai, Wang, Wei, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 64-74.
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:6  IF:5.2/4.5 | Submit date：2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, Rui P. Martins. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier[J]. IEEE Journal of Solid-State Circuits, 2021.
Authors:  Zihao Zheng;  Lai Wei;  Jorge Lagos;  Ewout Martens;  Yan Zhu; et al.
Favorite | TC[WOS]:10 TC[Scopus]:12  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype