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A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
Yang,Zunsong, Chen,Yong, Yang,Shiheng, Mak,Pui In, Martins,Rui P.. A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector[J]. IEEE Access, 2019, 8, 2222-2232.
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:19 TC[Scopus]:20  IF:3.4/3.7 | Submit date：2021/03/09
Cmos  Dual Loop  Phase-locked Loop (Pll)  Frequency Detector (Fd)  Phase Detector (Pd)  Figure-of-merit (Fom)  Millimeter (Mm)-wave  Voltage-to-current Converter (Vic)  Voltage-controlled Oscillator (Vco)  Divider-by-4  Dynamic Latch  
A 0.0018-mm2 153% locking-range CML-Based divider-by-2 with tunable self-resonant frequency using an auxiliary negative-gm Cell Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.0018-mm2 153% locking-range CML-Based divider-by-2 with tunable self-resonant frequency using an auxiliary negative-gm Cell[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3330-3339.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:12 TC[Scopus]:18  IF:5.2/4.5 | Submit date：2021/03/09
5g New Radio  Cmos  Current-mode-logic (Cml)  Divider-by-2  Injection Locking  Latch  Locking Range (Lr)  Negative-gm (Ng)  Phasor Diagram  Self-resonant Frequency (Fsr)  Sensitivity Curve (Sc)  Shunt Peaking  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui P. Martins. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(9), 3014-3026.
Authors:  Yong Chen;  Pui-In Mak;  Chirn Chye Boon;  Rui P. Martins
Favorite | TC[WOS]:26 TC[Scopus]:29  IF:5.2/4.5 | Submit date：2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin Journal article
Chen, Y., Mak, P. I., Boon, C.C., Martins, R. P.. A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 3014-3026.
Authors:  Chen, Y.;  Mak, P. I.;  Boon, C.C.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bandwidth (BW)  cross-quadrature clocking  data- dependent jitter (DDJ)  duobinary  multi-level signaling  CMOS  multiplexer (MUX)  figure-of-merit (FOM)  timing margin  latch  D-type flip-flop (DFF)  selector  
A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response Journal article
Zhao,Lei, Lu,Yan, Martins,Rui P.. A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response[J]. IEEE Solid-State Circuits Letters, 2018, 1(6), 154-157.
Authors:  Zhao,Lei;  Lu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:16  IF:2.2/2.0 | Submit date：2021/03/09
Continuous-time Comparator  Digital Low-dropout Regulator (Dldo)  Dynamic Logic  Transient Response  True Single-phase Clock (Tspc) Latch  
A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS Journal article
Chen, Yong, Mak, Pui-In, Boon, Chirn Chye, Martins, Rui P.. A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS[J]. IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2017, 27(9), 839-841.
Authors:  Chen, Yong;  Mak, Pui-In;  Boon, Chirn Chye;  Martins, Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:16  IF:2.9/3.0 | Submit date：2018/10/30
Cmos  Duobinary  Figure-of-merit (Fom)  Flip-flop (Ff)  Latch  Multiplexer (Mux)  Selector  Time-interleaved  
A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS Journal article
Liu, J., Chan, C.H., Sin, S. W., U, S.P., Martins, R. P.. A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 395-404.
Authors:  Liu, J.;  Chan, C.H.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite |   IF:0.5/0.3 | Submit date：2022/01/24
Flash ADC  time comparator  4x time-domain interpolation  SR-latch  
A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS Journal article
Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 16(4), 395-404.
Authors:  Jianwei Liu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2019/02/11
4x Time-domain Interpolation  Flash Adc  Sr-latch  Time Comparator