This letter presents a coarse-fine dual-loop digital low-dropout regulator (DLDO), with combined synchronous and asynchronous logics, designed and measured in a 28-nm bulk CMOS. We adopt a react-then-write two-step logic in the coarse loop for faster transient response. To further shorten the loop latency, we employ true single-phase clock dynamic latches in the coarse loop, and a self-biased continuous-time comparator for voltage droop detection. The proposed DLDO architecture achieves an FoM of 0.59 ps, with a load range of 5-25 mA under a 600-mV supply.