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A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment Journal article
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/10/10
Fast Locking  Frequency Synthesis  Frequency-locked Loop (Fll)  Low Jitter  Millimeter-wave (Mm-wave)  Phase-locked Loop (Pll)  Reference (Ref.) Spur  Sub-sampling Phase Detector (Sspd)  Voltage-controlled Oscillator (Vco)  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 0.32 × 0.12 mm2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout Journal article
Peng, Yatao, Benserhir, Jad, Castaneda, Mario, Fognini, Andreas, Bruschini, Claudio, Charbon, Edoardo. A 0.32 × 0.12 mm2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout[J]. IEEE Transactions on Microwave Theory and Techniques, 2024, 72(4), 2179-2192.
Authors:  Peng, Yatao;  Benserhir, Jad;  Castaneda, Mario;  Fognini, Andreas;  Bruschini, Claudio; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.1/4.2 | Submit date：2024/05/02
Bicmos  Cryogenic Temperatures  Low-noise Amplifiers  Sige Heterojunction Bipolar Transistor (Hbt)  Superconducting Single-photon Detectors  Timing Jitter  
A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller Journal article
Chen, Wen, Shu, Yiyang, Yin, Jun, Mak, Pui In, Gao, Xiang, Luo, Xun. A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Chen, Wen;  Shu, Yiyang;  Yin, Jun;  Mak, Pui In;  Gao, Xiang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2024/05/16
Detectors  Fast Locking  Frequency Locked Loops  Jitter  Jitter  Millimeter Wave (mm-Wave)  Phase Locked Loops  Phase Noise  Subsampling Phase-locked Loop (Sspll)  Voltage-controlled Oscillators  Wideband  Wideband  
Power-Efficient RF and mm-Wave VCOs/PLL Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:51-89
Authors:  Hao Guo;  Zunsong Yang;  Chee Cheow Lim;  Harikrishnan Ramiah;  Yatao Peng; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Harmonic Tuning  Inverse Class-f  Jitter  Millimeter Wave (mm-Wave)  Mode-switching  Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Subsampling  Voltage-controlled Oscillator (Vco)  
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:9  IF:2.8/2.8 | Submit date：2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii  
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference Journal article
Yu Duan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4799-4809.
Authors:  Yu Duan;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/01/30
Digital-regulated Supply Noise Cancellation (Dsnc)  Interference Reduction  Jitter  Phase Noise Cancellation (Pnc)  Phase-locked Loop  Phase-locked Loop (Pll)  Ring Voltage-controlled Oscillator (Rvco)  Supply Noise Suppression  
A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction Journal article
Xu, Tailong, Zhong, Shenke, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4774-4786.
Authors:  Xu, Tailong;  Zhong, Shenke;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2023/01/30
Gain-boosting  Low Jitter  Low Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Reference-sampling Phase Detector (Rspd)  Sampling Phase Detector (Spd)  Sub-sampling Phase Detector (Sspd)  Switched-capacitor Voltage Multiplier  
Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes - Fundamentals and Design Techniques Review article
2022
Authors:  Loo, Mikki How Wen;  Ramiah, Harikrishnan;  Lei, Ka Meng;  Lim, Chee Cheow;  Lai, Nai Shyan; et al.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:3.4/3.7 | Submit date：2022/09/09
Allan Deviation  Cmos  Figure-of-merit (Fom)  Frequency-locked-loop (Fll)  Internet-of-things (Iot)  Jitter  Phase Noise  Relaxation Oscillator (Rxo)  Ultra-low-power  Wakeup Timers  
A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and-250.3dB FoM Conference paper
Wen Chen, Yiyang Shu, Huizhen Jenny Qian, Jun Yin, Pui-In Mak, Xiang Gao, Xun Luo. A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and-250.3dB FoM[C], 2022, 159-162.
Authors:  Wen Chen;  Yiyang Shu;  Huizhen Jenny Qian;  Jun Yin;  Pui-In Mak; et al.
Favorite | TC[WOS]:8 TC[Scopus]:8 | Submit date：2023/01/30
Fast-locking  Jitter  Millimeter-wave (Mmw)  Sub-sampling Phase-locked Loop (Sspll)  Wideband