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16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
Chan, Chi-Hang, Zhu, Yan, Sin, Sai-Weng, Seng-Pan, U., Martins, Rui P., Maloberti, Franco. A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(8), 1966-1976.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.; et al.
Favorite | TC[WOS]:23 TC[Scopus]:24  IF:5.2/4.5 | Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS Journal article
Liu, J., Chan, C.H., Sin, S. W., U, S.P., Martins, R. P.. A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 395-404.
Authors:  Liu, J.;  Chan, C.H.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite |   IF:0.5/0.3 | Submit date：2022/01/24
Flash ADC  time comparator  4x time-domain interpolation  SR-latch  
A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS Journal article
Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 16(4), 395-404.
Authors:  Jianwei Liu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2019/02/11
4x Time-domain Interpolation  Flash Adc  Sr-latch  Time Comparator  
A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS Journal article
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2013, 48(9), 2154-2169.
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins; et al.
Favorite | TC[WOS]:17 TC[Scopus]:19  IF:4.6/5.6 | Submit date：2018/10/30
Analog-to-digital Conversion (Adc)  Calibration  Embedded Reference  Flash Adc  Folding  Low Power  
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators Conference paper
Wong S.-S., Chio U.-F., Chan C.-H., Choi H.-L., Sin S.-W., Seng-Pan U., Martins R.P.. A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators[C], 2011, 73-76.
Authors:  Wong S.-S.;  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.; et al.
Favorite | TC[Scopus]:22 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc  Flash Adc  Sar Adc  
Design and experimental verification of a power effective Flash-SAR subranging ADC Journal article
U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti. Design and experimental verification of a power effective Flash-SAR subranging ADC[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2010, 57(8), 607-611.
Authors:  U-Fat Chio;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:28 TC[Scopus]:34  IF:4.0/3.7 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Digital Error Correction (Dec)  Flash Adc  Sar Adc  Subranging Adc  
A Power Scalable 6-bit 1.2 GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier Conference paper
Wei, H.G., Chio, U. F., Zhu, Y., Sin, S.W., U, S.P., Martins, R. P.. A Power Scalable 6-bit 1.2 GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier[C], 2008.
Authors:  Wei, H.G.;  Chio, U. F.;  Zhu, Y.;  Sin, S.W.;  U, S.P.; et al.
Favorite |  | Submit date：2022/01/24
Flash ADC  Track-and-Hold  Power Scalable