| Status | 已發表Published |
| A Power Scalable 6-bit 1.2 GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier | |
Wei, H.G. ; Chio, U. F.; Zhu, Y.; Sin, S.W.; U, S.P.; Martins, R. P.
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| 2008-05-18 | |
| Source Publication | 2008 IEEE International Symposium on Circuits and Systems
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| Abstract | A power scalable 6-bit 1.2GS/s flash Analog-to-Digital Converter (ADC) is designed in 90nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is -0.9/+0.7 LSB and the INL is -0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pJ/conversion-step at Nyquist from 1.2V power supply. |
| Keyword | Flash ADC Track-and-Hold Power Scalable |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 38577 |
| Document Type | Conference paper |
| Collection | DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE |
| Recommended Citation GB/T 7714 | Wei, H.G.,Chio, U. F.,Zhu, Y.,et al. A Power Scalable 6-bit 1.2 GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier[C], 2008. |
| APA | Wei, H.G.., Chio, U. F.., Zhu, Y.., Sin, S.W.., U, S.P.., & Martins, R. P. (2008). A Power Scalable 6-bit 1.2 GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier. 2008 IEEE International Symposium on Circuits and Systems. |
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