English | 繁體

Search in the results

UM

Browse/Search Results:  1-10 of 15 Help

Selected(0)Clear Items/Page:    Sort:
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
High-Performance Oversampling ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:181-218
Authors:  Chi-Hang Chan;  Yan Zhu;  Liang Qi;  Sai Weng Sin;  Maurits Ortmanns; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Cmos  Continuous-time Dsm (Ct Dsm)  Delta-sigma Modulator (Dsm)  Noise Shaping (Ns)  Oversampling  Pipeline Sar Adc  Successive Approximation Register (Sar)  
L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs Journal article
Wang, Bo, Law, Man Kay, Schneider, Jens. L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs[J]. IEEE Transactions on Signal Processing, 2023, 71, 3229-3241.
Authors:  Wang, Bo;  Law, Man Kay;  Schneider, Jens
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:4.6/5.2 | Submit date：2024/02/22
Analog-to-digital Data Converter  Digital Linear Filter  Frequency Notch  Incremental Delta-sigma Adc  l  Reconstruction Filter  Thermal Noise Penalty  
Modelling and Analysis of ?S-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters Conference paper
Zhang, Xiongjie, Jiang, Yang, Law, Man Kay, Mak, Pui In, Martins, Rui P.. Modelling and Analysis of ?S-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters[C], 2022, 269-272.
Authors:  Zhang, Xiongjie;  Jiang, Yang;  Law, Man Kay;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2023/03/21
Dc-dc Converter  Dual-path Hybrid  Mash  Output Spectrum  Sigma-delta Modulator  Spur Reduction  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
Jiang, D., Sin, S. W., Qi, L., Wang, G., Martins, R. P.. Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 129-139.
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:16  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback Conference paper
Wang, B., Law, M. K., Bermak, A.. On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180394.
Authors:  Wang, B.;  Law, M. K.;  Bermak, A.
Favorite | TC[WOS]:0  | Submit date：2022/08/01
Incremental Delta-sigma Analog-to-digital Converter  Fully Differential Idc  1.5-bit Feedback  Modulator Codeword  Time-domain Analysis  
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator Conference paper
Junhao Liang, Sai-Weng Sin, U. Seng-Pan, Franco Maloberti, R.P. Martins, Hanjun Jiang. A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator[C]:IEEE, 2019, 309-312.
Authors:  Junhao Liang;  Sai-Weng Sin;  U. Seng-Pan;  Franco Maloberti;  R.P. Martins; et al.
Favorite | TC[WOS]:4 TC[Scopus]:7 | Submit date：2021/03/09
Ct Sigma Delta Ad Converter  Ecg  High Impedance  Non-invertering Integrator  Programmable Integrator  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite | TC[WOS]:48 TC[Scopus]:60  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase