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A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control Journal article
Yu, Kai, Yang, Shangru, Li, Sizhen, Huang, Mo. A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(4), 1754-1758.
Authors:  Yu, Kai;  Yang, Shangru;  Li, Sizhen;  Huang, Mo
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2024/05/02
Cmos Voltage Reference  Dibl Effect Compensation  Line Sensitivity  Power Supply Rejection Ratio  Self-biased  Ultra-low Power  
A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror Journal article
Yu, Kai, Chen, Jiyang, Li, Sizhen, Huang, Mo. A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(3), 1052-1056.
Authors:  Yu, Kai;  Chen, Jiyang;  Li, Sizhen;  Huang, Mo
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/02/22
Cmos Voltage Reference  Line Sensitivity  Power Supply Rejection Ratio  Quasi Self-cascode Current Mirror  Self-biased  
A 0.4-V 8400-μm2 Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect Journal article
Che, Chengyu, Lei, Ka Meng, Martins, Rui P., Mak, Pui In. A 0.4-V 8400-μm2 Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(10), 3822-3826.
Authors:  Che, Chengyu;  Lei, Ka Meng;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.0/3.7 | Submit date：2023/11/01
Analog Circuit  Deep-submicron Cmos  Layout-dependent Effect (Lde)  Ultra-low-voltage  Voltage Reference  Well-proximity Effect (Wpe)  
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:9  IF:2.8/2.8 | Submit date：2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
Huang, Yunbo, Chen, Yong, Jiao, Hailong, Mak, Pui In, Martins, Rui P.. A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(9), 3093-3097.
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:20 TC[Scopus]:19  IF:4.0/3.7 | Submit date：2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
Zunsong Yang, Yong Chen, Pui In Mak, Rui P. Martins. A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68(6), 2307-2316.
Authors:  Zunsong Yang;  Yong Chen;  Pui In Mak;  Rui P. Martins
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Cmos  Current-reuse Sampling Phase Detector (Crs-pd)  Integrated Jitter  Loop Filter (Lf)  Master-slave Sampling Filter (Mssf)  Master-slave Sampling Phase Detector (Mss-pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Type-i  Type-ii  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM[J]. IEEE Solid-State Circuits Letters, 2020, 3, 494-497.
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:18 TC[Scopus]:19 | Submit date：2021/03/09
Cmos  In-band Phase Noise (Pn)  Narrow-pulse-sampling (Nps)  Phase-locked Loop (Pll)  Reference (Ref) Spur  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity Journal article
Lin,Jie, Wang,Lidan, Zhan,Chenchang, Lu,Yan. A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(10), 1653-1657.
Authors:  Lin,Jie;  Wang,Lidan;  Zhan,Chenchang;  Lu,Yan
Favorite | TC[WOS]:39 TC[Scopus]:46  IF:4.0/3.7 | Submit date：2021/03/11
Cmos Voltage Reference  Line Sensitivity  Low Power  Low Voltage  Subthreshold  
0.45-V 5.4-nW switched-capacitor bandgap reference with intermittent operation and improved supply immunity Journal article
Luo, Z., Lu, Y., Martins, R. P.. 0.45-V 5.4-nW switched-capacitor bandgap reference with intermittent operation and improved supply immunity[J]. Electronics Letters, 2018, 1154-1156.
Authors:  Luo, Z.;  Lu, Y.;  Martins, R. P.
Favorite |   IF:0.7/0.9 | Submit date：2022/01/25
Charge Pump Circuits  Cmos Integrated Circuits  Low-power Electronics  Reference Circuits  Sample And Hold Circuits  Switched Capacitor Networks  Voltage Multipliers