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Status | 已發表Published |
A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity | |
Lin,Jie1,2; Wang,Lidan1; Zhan,Chenchang1; Lu,Yan2 | |
2019-10-01 | |
Source Publication | IEEE Transactions on Circuits and Systems II: Express Briefs |
ISSN | 1549-7747 |
Volume | 66Issue:10Pages:1653-1657 |
Abstract | This brief presents a CMOS voltage reference for Internet-of-Things applications, which requires ultra-low power and high insensitivity to voltage variation from ambient energy harvesting. This brief proposed a novel self-regulating circuit to significantly diminish the line sensitivity (LS) of reference voltage to supply voltage without using any amplifiers or passive components. All the transistors in this design work in subthreshold region for low voltage and low power operation. The proposed design is fabricated in a standard 0.18-μm CMOS process. The measurement results show that, the proposed circuit could provide an average reference voltage of 151 mV with a variation coefficient of 0.84 %. It achieves a LS of 0.0154 %/V when the supply voltage varies from 0.5 V to 1.8 V. The measured power supply ripple rejections at 10 Hz, 1 kHz, 100 kHz, and 1 MHz are-73.0 dB,-49.4 dB,-49.6 dB, and-49.8 dB, respectively. The average temperature coefficient is measured as 89.83 ppm/°C with a standard deviation of 12.19 ppm/°C in a temperature range from-40 °C to +125 °C. The consumed power of this design is 1 nW with a minimum supply voltage of 0.4 V at room temperature, and the active area is 0.005 mm. |
Keyword | Cmos Voltage Reference Line Sensitivity Low Power Low Voltage Subthreshold |
DOI | 10.1109/TCSII.2019.2920693 |
URL | View the original |
Language | 英語English |
WOS ID | WOS:000489738500011 |
Scopus ID | 2-s2.0-85072761397 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS |
Corresponding Author | Zhan,Chenchang; Lu,Yan |
Affiliation | 1.Department of Electrical and Electronic Engineering,Southern University of Science and Technology,Shenzhen,518055,China 2.State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,Macao |
First Author Affilication | University of Macau |
Corresponding Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Lin,Jie,Wang,Lidan,Zhan,Chenchang,et al. A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(10), 1653-1657. |
APA | Lin,Jie., Wang,Lidan., Zhan,Chenchang., & Lu,Yan (2019). A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity. IEEE Transactions on Circuits and Systems II: Express Briefs, 66(10), 1653-1657. |
MLA | Lin,Jie,et al."A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity".IEEE Transactions on Circuits and Systems II: Express Briefs 66.10(2019):1653-1657. |
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