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A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:IEEE, 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
Zhang, Ran, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Xu, Dengke, Zhao, Weibing, Martins, R. P., Maloberti, Franco, Sin, Sai Weng. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C], 2024.
Authors:  Zhang, Ran;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang;  Xu, Dengke; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/08/05
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward Journal article
Zhao,Shulin, Guo,Mingqiang, Qi,Liang, Xu,Dengke, Wang,Guoxing, Martins,Rui P., Sin,Sai Weng. A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10), 2722-2732.
Authors:  Zhao,Shulin;  Guo,Mingqiang;  Qi,Liang;  Xu,Dengke;  Wang,Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2023/08/03
Error-feedforward (Ff)  Midway Error-feedback (Fb)  Noise Transfer Function (Ntf) Peaking  Offset Reduction  Redundancy  Time-interleaving Noise-shaping Successive Approximation Register (Ns-sar)  
A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction Conference paper
Zhao, Shulin, Guo, Mingqiang, Sin, Sai Weng, Qi, Liang, Xu, Dengke, Wang, Guoxing, Martins, Rui P.. A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction[C]:IEEE, 2022.
Authors:  Zhao, Shulin;  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke; et al.
Adobe PDF | Favorite | TC[Scopus]:1 | Submit date：2023/03/06
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
Guo, Mingqiang, Sin, Sai Weng, Qi, Liang, Xu, Dengke, Wang, Guoxing, Martins, Rui P.. Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(6), 2564 - 2569.
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2022/05/17
Adc  Time-interleaved  Timing Mismatch  Background  Calibration.