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A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLYCurrent Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density Conference paper
Ma, Qiaobo, Li, Huihua, Shi, Jiahao, Jiang, Yang, Martins, Rui, Mak, Pui In. A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLYCurrent Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Ma, Qiaobo;  Li, Huihua;  Shi, Jiahao;  Jiang, Yang;  Martins, Rui; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUTAugmentation Conference paper
Li, Huihua, Ma, Qiaobo, Jiang, Yang, Martins, Rui, Mak, Pui In. A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUTAugmentation[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 22-2.
Authors:  Li, Huihua;  Ma, Qiaobo;  Jiang, Yang;  Martins, Rui;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation Conference paper
Shen, Xinyu, Zhang, Zhao, Chen, Yong, Li, Yixi, Zhang, Yidan, Li, Guike, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Chen, Yong;  Li, Yixi;  Zhang, Yidan; et al.
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Temperature Sensors  Phase Noise  Linearity  Voltage  Detectors  Jitter  Delay Lines  
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS Conference paper
Qin, Xinyu, Jin, Yichen, Wang, Guoxing, Sin, Sai Weng, Ortmanns, Maurits, Lian, Yong, Qi, Liang. A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 199537.
Authors:  Qin, Xinyu;  Jin, Yichen;  Wang, Guoxing;  Sin, Sai Weng;  Ortmanns, Maurits; et al.
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A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC Conference paper
He, Pengyu, Zhao, Yuanzhe, Xie, Heng, Wang, Yang, Yin, Shouyi, Li, Li, Zhu, Yan, Martins, R. P., Chan, Chi Hang, Zhang, Minglei. A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 199537.
Authors:  He, Pengyu;  Zhao, Yuanzhe;  Xie, Heng;  Wang, Yang;  Yin, Shouyi; et al.
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A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit Control Conference paper
PENG YATAO, Jad Benserhir, Yating Zou, Edoardo Charbon. A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit Control[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 32-4.
Authors:  PENG YATAO;  Jad Benserhir;  Yating Zou;  Edoardo Charbon
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Temperature  Superconducting Integrated Circuits  Qubit  Linearity  Cryogenics  Superconducting Filters  Superconducting Device Noise  
A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs Conference paper
Mao, Xiangyu, Huang, Junwei, Tong, Zhiguo, Martins, Rui, Lu, Yan. A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 9-4.
Authors:  Mao, Xiangyu;  Huang, Junwei;  Tong, Zhiguo;  Martins, Rui;  Lu, Yan
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Transient Response  Buck Converters  Regulators  Multicore Processing  Capacitors  Power System Dynamics  Inductors  
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC Conference paper
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC[C], 2012.
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:0 TC[Scopus]:10 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Time-interleaved  Sar Adc  Two-step Adc